1 U. Schlichtmann, "Tomorrows high-quality SoCs require high-quality embedded memories today" 2002
2 Y. K. Kim, "Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method, U. S. Patent 7,184,331"
3 S. H. Kang, "Redundancy circuit in semiconductor memory device, U.S. Patent 7,257,037"
4 M. Richter, "New Linear SEC-DED Codes with Reduced Triple Error Miscorrection Probability" 37-42, 2008
5 Jeong-In Park, "High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture" 대한전자공학회 10 (10): 193-202, 2010
6 D. K. Pradhan, "Fault-Tolerant Computer System Design" Prentice Hall 1996
7 R. Datta, "Exploiting Unused Spare Columns to Improve Memory ECC" 47-52, 2009
8 R. Hamming, "Error Correcting and Error Detecting Codes" 29 : 147-160, 1950
9 W. Peterson, "Error Correcting Codes" MIT Press 1972
10 Y. Zorian, "Embedded-Memory Test and Repair: Infrastructure IP for SOC Yield" 20 (20): 58-66, 2003
1 U. Schlichtmann, "Tomorrows high-quality SoCs require high-quality embedded memories today" 2002
2 Y. K. Kim, "Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method, U. S. Patent 7,184,331"
3 S. H. Kang, "Redundancy circuit in semiconductor memory device, U.S. Patent 7,257,037"
4 M. Richter, "New Linear SEC-DED Codes with Reduced Triple Error Miscorrection Probability" 37-42, 2008
5 Jeong-In Park, "High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture" 대한전자공학회 10 (10): 193-202, 2010
6 D. K. Pradhan, "Fault-Tolerant Computer System Design" Prentice Hall 1996
7 R. Datta, "Exploiting Unused Spare Columns to Improve Memory ECC" 47-52, 2009
8 R. Hamming, "Error Correcting and Error Detecting Codes" 29 : 147-160, 1950
9 W. Peterson, "Error Correcting Codes" MIT Press 1972
10 Y. Zorian, "Embedded-Memory Test and Repair: Infrastructure IP for SOC Yield" 20 (20): 58-66, 2003
11 I. Kim, "Built In Self Repair for Embedded High Density SRAM" 1112-1119, 1998
12 W. Jeong, et al, "An Advanced BIRA for Memories with an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 29 (29): 2014-2026, 2010
13 M. Y. Hsiao, "A Class of Optimal Minimum Oddweight-column SEC-DED codes" 14 : 395-401, 1970