This study focuses on optimizing the Kogge - Stone Adder (KSA) to reduce power usage while maintaining performance. We propose a new parallel prefix adder structure EPCA (Energy-efficient Parallel Computational) that minimizes the number of gates, lea...
This study focuses on optimizing the Kogge - Stone Adder (KSA) to reduce power usage while maintaining performance. We propose a new parallel prefix adder structure EPCA (Energy-efficient Parallel Computational) that minimizes the number of gates, leading to lower power consumption Simulations on 64-bit versions of the Ripple Carry Adder (RCA), KSA, and the EPCA using the design compiler show that the EPCA reduces power consumption by 45.8% compared to the KSA, with only a 18% increase over the RCA. When it comes to delay, the EPCA achieved around 1.8 times faster performance than the RCA, though it was roughly 2.5 times slower compared to the KSA. The power reduction is due to fewer leaf cells and wires. However, the EPCA has a longer critical path, increasing delay for 64-bit computations. This study highlights the trade-off between power efficiency and delay in high-bit computations.