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    RISS 인기검색어

      Performance analysis of novel fault‐tolerant multilevel inverter with a pristine methodology for fast and exhaustive real‐time failure of switches

      한글로보기

      https://www.riss.kr/link?id=O112775081

      • 저자
      • 발행기관
      • 학술지명
      • 권호사항
      • 발행연도

        2021년

      • 작성언어

        -

      • Print ISSN

        0098-9886

      • Online ISSN

        1097-007X

      • 등재정보

        SCI;SCIE;SCOPUS

      • 자료형태

        학술저널

      • 수록면

        4046-4069   [※수록면이 p5 이하이면, Review, Columns, Editor's Note, Abstract 등일 경우가 있습니다.]

      • 구독기관
        • 전북대학교 중앙도서관  
        • 성균관대학교 중앙학술정보관  
        • 부산대학교 중앙도서관  
        • 전남대학교 중앙도서관  
        • 제주대학교 중앙도서관  
        • 중앙대학교 서울캠퍼스 중앙도서관  
        • 인천대학교 학산도서관  
        • 숙명여자대학교 중앙도서관  
        • 서강대학교 로욜라중앙도서관  
        • 충남대학교 중앙도서관  
        • 한양대학교 백남학술정보관  
        • 이화여자대학교 중앙도서관  
        • 고려대학교 도서관  
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      부가정보

      다국어 초록 (Multilingual Abstract)

      Multilevel inverter (MLI) provides a high power density, though the number of devices increases the chances of failures increases, reducing the reliability of power converter. It is essential to detect, isolate, and reconfigure the faults which arises in MLI. The research proposed here is capable of accomplishing the complete fault tolerance against single and multiple devices for both open circuit and short circuit faults. The control algorithm for operation of single‐pole‐double‐throw (SPDT) relays. This methodology is capable of completely preserving the normal operating condition in post‐fault condition also. The output voltage waveform matches by voltage sensors connected across load, and the controllers sense the faults originated from the variation in the look‐up‐table (LUT) and also categorize the nature of the faults. Field‐programmable gate array (FPGA)‐based controller sends a command signal through SPDT to isolate the faulty switches by redundant switches. In this way, the output power across the load is preserved. This research article also covers the comparative study that is made with the existing fault‐tolerant structures. The reliability comparison shows the better performance indices over conventional cascaded H‐bridge (CHB) inverter. The simulation and experimental results validate the effectiveness of control methodology to achieve complete fault tolerance.
      The proposed fault‐tolerant topology aims to detect, isolate, and reconfigure to healthy waveform with redundant switches. The control scheme uses single‐pole‐double‐throw relay toggles to reconfigure healthy waveform using redundant switch(es). The control algorithm developed in Cyclone V is fast, exhaustive, and capable of clearing both open and short circuit fault for both single and multiple switch failure. The classification of abovementioned fault is studied using unique behavior observed from look‐up‐table by comparing the reference/healthy and fault waveform.
      번역하기

      Multilevel inverter (MLI) provides a high power density, though the number of devices increases the chances of failures increases, reducing the reliability of power converter. It is essential to detect, isolate, and reconfigure the faults which arises...

      Multilevel inverter (MLI) provides a high power density, though the number of devices increases the chances of failures increases, reducing the reliability of power converter. It is essential to detect, isolate, and reconfigure the faults which arises in MLI. The research proposed here is capable of accomplishing the complete fault tolerance against single and multiple devices for both open circuit and short circuit faults. The control algorithm for operation of single‐pole‐double‐throw (SPDT) relays. This methodology is capable of completely preserving the normal operating condition in post‐fault condition also. The output voltage waveform matches by voltage sensors connected across load, and the controllers sense the faults originated from the variation in the look‐up‐table (LUT) and also categorize the nature of the faults. Field‐programmable gate array (FPGA)‐based controller sends a command signal through SPDT to isolate the faulty switches by redundant switches. In this way, the output power across the load is preserved. This research article also covers the comparative study that is made with the existing fault‐tolerant structures. The reliability comparison shows the better performance indices over conventional cascaded H‐bridge (CHB) inverter. The simulation and experimental results validate the effectiveness of control methodology to achieve complete fault tolerance.
      The proposed fault‐tolerant topology aims to detect, isolate, and reconfigure to healthy waveform with redundant switches. The control scheme uses single‐pole‐double‐throw relay toggles to reconfigure healthy waveform using redundant switch(es). The control algorithm developed in Cyclone V is fast, exhaustive, and capable of clearing both open and short circuit fault for both single and multiple switch failure. The classification of abovementioned fault is studied using unique behavior observed from look‐up‐table by comparing the reference/healthy and fault waveform.

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