This paper proposes a low power small size design of the KB1 block cipher algorithm aiming to portable applications such as RFIDs and PDAs. The KB1 algorithm comprises a modified Feistel structure processing 64 bits data with 128 bits keys. The key ge...
This paper proposes a low power small size design of the KB1 block cipher algorithm aiming to portable applications such as RFIDs and PDAs. The KB1 algorithm comprises a modified Feistel structure processing 64 bits data with 128 bits keys. The key generation employs an on-th-fly scheme, where key generation and encryption can be processed simultaneously. The design has been synthesized based on Hynix 0.35㎛ CMOS process resulting in less than 5,100 equivalent gates. One single encryption using 100kHz clock consumes 86㎼ which is small enough for using ultra low power applications of a RFID type.