TNMIN와 TMAX 회로를 이용한 3치 D플립-플롭 설계 = The Design of Ternary D-Flip-Flop using TNMIN and TMAX Circuits

다국어 초록 (Multilingual Abstract)

This paper discusses ternary logic gate and ternary D flip-flop. The ternary logic gates consist of n-channel pass transistors and neuron MOS threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The neuron MOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level neuron MOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35 process parameter, and also represent HSPICE simulation result.