고집적 반도체 패키징을 위한 Seed 및 Seedless층 TSV의 Cu 충전 및 하이브리드 본딩 = Cu Filling into Seed and Seedless Layered Through-Silicon-Via and Hybrid Bonding for High-Density Semiconductor Packaging

다국어 초록 (Multilingual Abstract)

Through-silicon via (TSV) filling is indispensable for three-dimensional semiconductor packaging. Conventional processes rely on PVD (physical vapor deposition) or ALD (atomic layer deposition) seed layer deposition followed by copper electroplating, but these approaches face limitations in productivity and conformality. ALD and ELD (electroless deposition) have been investigated as seed-based approaches to overcome poor step coverage, while seedless strategies have also been proposed including additive-assisted electroplating, electroless alloy layers, metallic nanowires, and conductive pastes. These methods have demonstrated void-free or seam-free fills under specific conditions, yet challenges remain in achieving uniform superconformal filling across dense arrays, suppressing copper oxidation and interfacial contamination during rinsing/drying, and guaranteeing long-term reliability under thermomechanical cycling, electromigration, and humidity bias. In parallel, hybrid bonding has emerged as an alternative to thermo-compression bonding, where TSV filling performance, CMP (chemical mechanical polishing) planarization, and interface activation are crucial to reliable bonding. An integrated research approach incorporating both seed- and seedless-based TSV filling together with hybrid bonding provides a credible pathway to reliable three-dimensional stacking for high-bandwidth memory and artificial intelligence applications.