웨이퍼 얼라인먼트를 위한 고속 템플릿 매칭 시스템 FPGA 구현

다국어 초록 (Multilingual Abstract)

In this paper, we propose a hardware structure for a template matching system based on the NCC (Normalized Cross Correlation) algorithm for wafer alignment. Since the existing NCC algorithm requires a large amount of repetitive operations on consecutive pixels, processing time tends to be delayed when implemented only in the PS area of the FPGA. In order to improve these areas, within the template matching system, parts with a lot of formula processing and poor continuity of memory access coordinate values are processed in the PS area, and a high-speed template matching system implemented in the PL area with cross correlation and normalization that enables high-speed parallel processing. It is proposed as an alternative solution. In this paper, we implement a template matching system using the Xilinx Ultrascale+ MPSoC ZCU104 FPGA board and present the results of verifying the improvement in processing speed using the source image and target image extracted from wafer vision inspection equipment.