A 1.9&#x2013;3.8 GHz <tex> $\Delta \Sigma$</tex> Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

다국어 초록 (Multilingual Abstract)

<P>A fast and high-precision all-digital automatic calibration circuit that is highly suited for <TEX>$\Delta \Sigma$</TEX> fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-<TEX>$f_{\rm REF}$</TEX> frequency resolution of <TEX>$f_{\rm REF}/k$</TEX> in a time period of <TEX>$k\cdot T_{\rm REF}$</TEX>. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain <TEX>$K_{\rm VCO}$</TEX> and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate <TEX>$\Delta \Sigma$</TEX> modulator to achieve sub- <TEX>$f_{\rm REF}$</TEX> calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9–3.8 GHz <TEX>$\Delta \Sigma$</TEX> fractional-N synthesizer is implemented in 0.13 <TEX>$\mu$</TEX>m CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1–6.0 <TEX>$\mu$</TEX>s with <TEX>${\pm}2\hbox{\%}$</TEX> accuracy and the VCO frequency calibration is completed in 1.225–4.025 <TEX>$\mu$</TEX>s, all across the entire octave tuning range.</P>