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다국어 초록 (Multilingual Abstract)

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field?Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

목차 (Table of Contents)

Abstract
1. 서론
2. 설계 조건 및 개발 플랫폼 구현
3. MLP_SOC
4. 구현 및 검증

Abstract
1. 서론
2. 설계 조건 및 개발 플랫폼 구현
3. MLP_SOC
4. 구현 및 검증
5. 결론
참고문헌
저자소개

참고문헌 (Reference)

1 H. Nakajima, "Portable Translator capable of Recognizing Characters on Signboard and Menu Captured by built‐in camera" 61-64, 2005

2 "MT9V112 manual, Micron Technology Inc"

3 "LEON2 processor user’s manual"

4 J. M. Zurada, "Introduction to Artificial Neural Systems" PWS publishing company 1992

5 E. M. Oritigosa, "Hardware description of multi layer perceptrons with different abstraction levels" 30 : 435-444, 2006

6 Pentland, "Face recognition for smart environments" 33 (33): 50-55, 2000

7 Theocharides, G. Link, "Embedded Hardware Face Detection" 2004

8 S. Vitabile, "Efficient MLP Digital Implementation on FPGA" 2005

9 T. Schoenauer, "Digital Neurohardware : Principals and Perspectives" 101-106, 1998

10 M. Shabiul, "Design and Implementation of Discrete Cosine Transform Chip for Digital Comsumer Products" 52 (52): 998-1003, 2006

1 H. Nakajima, "Portable Translator capable of Recognizing Characters on Signboard and Menu Captured by built‐in camera" 61-64, 2005

2 "MT9V112 manual, Micron Technology Inc"

3 "LEON2 processor user’s manual"

4 J. M. Zurada, "Introduction to Artificial Neural Systems" PWS publishing company 1992

5 E. M. Oritigosa, "Hardware description of multi layer perceptrons with different abstraction levels" 30 : 435-444, 2006

6 Pentland, "Face recognition for smart environments" 33 (33): 50-55, 2000

7 Theocharides, G. Link, "Embedded Hardware Face Detection" 2004

8 S. Vitabile, "Efficient MLP Digital Implementation on FPGA" 2005

9 T. Schoenauer, "Digital Neurohardware : Principals and Perspectives" 101-106, 1998

10 M. Shabiul, "Design and Implementation of Discrete Cosine Transform Chip for Digital Comsumer Products" 52 (52): 998-1003, 2006

11 K. Mathia, "Benchmarking and MIMD Neural Network Processor" 1996

12 P. G. D. Valle, "Application of FPGA Emulation to SoC Floorplan and Packaging Exploration" 236-240, 2007

13 A. Rosado‐Munoz, "An IP Core and GUI Implementing Multilayer Perceptron with a Fuzzy Activation Function on Configurable Logic Devices" 14 (14): 1678-1694, 2008

14 M. Brogatti, "A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O" 38 : 521-529, 2003

15 M. Pormann, "A Reconfigurable SOM Hardware Accelerator" 337-342, 2002