1 G. Leung, "Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs" 33 (33): 767-769, 2012
2 X. Sun, "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap" 29 (29): 491-493, 2008
3 H.-S. Wong, "Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFETs" 705-708, 1993
4 H. Nam, "The design optimization and variation study of segmented-channel MOSFET using HfO2 or SiO2 trench isolation" 22-24, 2013
5 C. Shin, "Study of random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFETs" 56 (56): 1538-1542, 2009
6 H. Nam, "Study of high-k/metal-gate work-function variation using Rayleigh distribution" 34 (34): 532-535, 2013
7 H. Nam, "Study of high-k/metal-gate work function variation in FinFET: the modified RGG concept" 34 (34): 1560-1562, 2013
8 M. Aldegunde, "Study of discrete doping induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulations" 33 (33): 194-196, 2012
9 A. Khakifirooz, "Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS" 117-118, 2012
10 X. Wang, "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: a fullscale 3-D simulation scaling study" 58 (58): 2293-2301, 2011
1 G. Leung, "Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs" 33 (33): 767-769, 2012
2 X. Sun, "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap" 29 (29): 491-493, 2008
3 H.-S. Wong, "Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFETs" 705-708, 1993
4 H. Nam, "The design optimization and variation study of segmented-channel MOSFET using HfO2 or SiO2 trench isolation" 22-24, 2013
5 C. Shin, "Study of random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFETs" 56 (56): 1538-1542, 2009
6 H. Nam, "Study of high-k/metal-gate work-function variation using Rayleigh distribution" 34 (34): 532-535, 2013
7 H. Nam, "Study of high-k/metal-gate work function variation in FinFET: the modified RGG concept" 34 (34): 1560-1562, 2013
8 M. Aldegunde, "Study of discrete doping induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulations" 33 (33): 194-196, 2012
9 A. Khakifirooz, "Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS" 117-118, 2012
10 X. Wang, "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: a fullscale 3-D simulation scaling study" 58 (58): 2293-2301, 2011
11 A. Asenov, "Simulation of statistical variability in nano MOSFETs" 86-87, 2007
12 B. Ho, "Segmented-channel Si1−xGex/Si pMOSFET for improved ION and reduced variability" 167-168, 2012
13 N. Sano, "Role of long-range and short-range coulomb potentials in threshold characteristics under discrete dopants in sub-0.1 um Si-MOSFETs" 275-278, 2000
14 K. J. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS" 471-474, 2007
15 A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D “atomistic” simulation study" 45 (45): 2505-2513, 1998
16 C. Shin, "Quasi-planar bulk CMOS technology for improved SRAM scalability" 65-66 : 184-190, 2011
17 C. Shin, "Quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node" 58 (58): 1846-1854, 2011
18 A. R. Brown, "Poly-Si-Gate-related variability in decananometer MOSFETs with conventional architecture" 54 (54): 3056-3063, 2007
19 C. W. Lee, "Performance estimation of junctionless multigate transistors" 54 (54): 97-103, 2010
20 C. Shin, "Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node" 57 (57): 1301-1309, 2010
21 J. P. Colinge, "Nanowire transistors without junctions" 5 : 225-229, 2010
22 M. J. M. Pelgrom, "Matching properties of MOS transistors" 24 (24): 1433-1440, 1989
23 Z. Guo, "Large-scale SRAM variability characterization in 45 nm CMOS" 44 (44): 3174-3192, 2009
24 A. Asenov, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness" 50 (50): 1254-1260, 2003
25 "International Technology Roadmap for Semiconductors (ITRS)"
26 A. Asenov, "Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study" 48 (48): 722-729, 2001
27 C. Shin, "Impact of using doublepatterning versus single patterning on threshold voltage (VTH) variation in quasi-planar tri-gate bulk MOSFETs" 34 (34): 578-580, 2013
28 K. Ohmori, "Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates" 409-412, 2008
29 K. Bernstein, "High-performance CMOS variability in the 65-nm regime and beyond" 50 (50): 433-449, 2006
30 H. F. Dadgour, "Grain-orientation induced work function variation in nanoscale metal-gate transistors – Part I:modeling, analysis, and experimental validation" 57 (57): 2504-2514, 2010
31 B. Ho, "Fabrication of Si1−xGex/Si pMOSFETs Using Corrugated Substrates for Improved ION and Reduced Layout-Width Dependence" 60 (60): 153-158, 2013
32 C. H. Park, "Electrical characteristics of 20-nm junctionless Si nanowire transistors" 73 : 7-10, 2012
33 I. J. Park, "Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs" 10 (10): 20130108-, 2013
34 Y. Li, "Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS" 55 (55): 1449-1455, 2008
35 A. E. Carlson, "Device and circuit techniques for reducing variation in nanoscale SRAM" Univ. California Berkeley 2008
36 R. H. Dennard, "Design of ion-implanted MOSFET’s with very small physical dimensions" 9 (9): 256-268, 1974
37 G. E. Moore, "Cramming more components onto integrated circuits" 86 (86): 82-85, 1998
38 H. Nam, "Comparative study in workfunction variation: Gaussian vs. Rayleigh distribution for grain size" 10 (10): 20130109-, 2013
39 Y. Zhao, "Characterization of amorphous and crystalline rough surface: principles and applications" Academic Press 2001
40 D. Reid, "Analysis of threshold voltage distribution due to random dopants: A 100,000-sample 3-D simulation study" 56 (56): 2255-2263, 2009
41 C. Auth, "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, selfaligned contacts and high density MIM capacitors" 131-132, 2012