1 B. Razavi, "The role of PLLs in future wireline transmitters" 56 (56): 1786-1793, 2009
2 J.-Y. Ihm, "Stability analysis of bang-bang phase-locked loops for clock and data recovery systems" 60 (60): 1-5, 2013
3 "Specification of high-bandwidth digital content protection system, ver. 2.2"
4 K.-S. Kwak, "Power-reduction technique using a single edge-tracking clock for multiphase clock and data recovery circuits" 61 (61): 239-243, 2014
5 S. Tertinek, "Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter" 58 (58): 331-335, 2011
6 A. Hajimiri, "Noise in Phase-Locked Loops" 1-6, 2001
7 G. Harald, "New multimedia interface MHL market status and technology" 2012
8 "Mobile-high-definition link specification, ver. 2.0"
9 "Mobile MHL Transmitters" Lattice Semiconductor
10 "High-definition multimedia interface specification, ver. 1.4b"
1 B. Razavi, "The role of PLLs in future wireline transmitters" 56 (56): 1786-1793, 2009
2 J.-Y. Ihm, "Stability analysis of bang-bang phase-locked loops for clock and data recovery systems" 60 (60): 1-5, 2013
3 "Specification of high-bandwidth digital content protection system, ver. 2.2"
4 K.-S. Kwak, "Power-reduction technique using a single edge-tracking clock for multiphase clock and data recovery circuits" 61 (61): 239-243, 2014
5 S. Tertinek, "Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter" 58 (58): 331-335, 2011
6 A. Hajimiri, "Noise in Phase-Locked Loops" 1-6, 2001
7 G. Harald, "New multimedia interface MHL market status and technology" 2012
8 "Mobile-high-definition link specification, ver. 2.0"
9 "Mobile MHL Transmitters" Lattice Semiconductor
10 "High-definition multimedia interface specification, ver. 1.4b"
11 A. Kobayashi, "DisplayPort ver. 1.2 overview" 2010
12 P. Latha, "Color Space Converter"
13 P. S. Sahni, "An equalizer with controllable transfer function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort receivers in 28-nm UTBB-FDSOI" 24 (24): 2803-2807, 2016
14 P. K. Hanumolu, "A wide-tracking range clock and data recovery circuit" 43 (43): 425-439, 2006
15 S. Kim, "A dual PFD phase rotating multi-phase PLL for 5 Gbps PCI express gen2 multi-lane serial link receiver in $0.13{\mu}m$ CMOS" 234-235, 2007
16 C. -H. Park, "A Low-Noise, 900-MHz VCO in $0.6-{\mu}m$ CMOS" 34 (34): 586-591, 1999
17 H. Kim, "A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology" 546-547, 2016
18 "A DTV Profile for Uncompressed High Speed Digital Interfaces, CTA-861-G"
19 C.-C. Ju, "A 4Kx2K @60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver" 2014
20 Y.-B. Luo, "A 250 Mb/s-to-3.4 Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer" 190-191, 2009