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      KCI등재 SCIE SCOPUS

      A HDMI-to-MHL Video Format Conversion System-on-Chip (SoC) for Mobile Applications

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      https://www.riss.kr/link?id=A105527256

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      다국어 초록 (Multilingual Abstract)

      The high-definition multimedia interface (HDMI) output of the application processor (AP) of a mobile handset is converted to a mobile highdefinition link (MHL) signal by a video format conversion system-on-chip (SoC). The MHL signal is then delivered ...

      The high-definition multimedia interface (HDMI) output of the application processor (AP) of a mobile handset is converted to a mobile highdefinition link (MHL) signal by a video format conversion system-on-chip (SoC). The MHL signal is then delivered over a 5-pin cable to a television (TV) or monitor, allowing the audio/video (AV) contents of a mobile handset to be displayed on a large screen. The functionalities and performance of the HDMI-to- MHL video format conversion SoC implemented in a 130-nm CMOS technology have been verified by the compliance tests specified by the HDMI and MHL standards.

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      목차 (Table of Contents)

      • Abstract
      • I. INTRODUCTION
      • II. ARCHITECTURE AND CIRCUIT IMPLEMENTATIONS
      • III. EXPERIMENTAL RESULTS
      • IV. CONCLUSIONS
      • Abstract
      • I. INTRODUCTION
      • II. ARCHITECTURE AND CIRCUIT IMPLEMENTATIONS
      • III. EXPERIMENTAL RESULTS
      • IV. CONCLUSIONS
      • REFERENCES
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      참고문헌 (Reference)

      1 B. Razavi, "The role of PLLs in future wireline transmitters" 56 (56): 1786-1793, 2009

      2 J.-Y. Ihm, "Stability analysis of bang-bang phase-locked loops for clock and data recovery systems" 60 (60): 1-5, 2013

      3 "Specification of high-bandwidth digital content protection system, ver. 2.2"

      4 K.-S. Kwak, "Power-reduction technique using a single edge-tracking clock for multiphase clock and data recovery circuits" 61 (61): 239-243, 2014

      5 S. Tertinek, "Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter" 58 (58): 331-335, 2011

      6 A. Hajimiri, "Noise in Phase-Locked Loops" 1-6, 2001

      7 G. Harald, "New multimedia interface MHL market status and technology" 2012

      8 "Mobile-high-definition link specification, ver. 2.0"

      9 "Mobile MHL Transmitters" Lattice Semiconductor

      10 "High-definition multimedia interface specification, ver. 1.4b"

      1 B. Razavi, "The role of PLLs in future wireline transmitters" 56 (56): 1786-1793, 2009

      2 J.-Y. Ihm, "Stability analysis of bang-bang phase-locked loops for clock and data recovery systems" 60 (60): 1-5, 2013

      3 "Specification of high-bandwidth digital content protection system, ver. 2.2"

      4 K.-S. Kwak, "Power-reduction technique using a single edge-tracking clock for multiphase clock and data recovery circuits" 61 (61): 239-243, 2014

      5 S. Tertinek, "Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter" 58 (58): 331-335, 2011

      6 A. Hajimiri, "Noise in Phase-Locked Loops" 1-6, 2001

      7 G. Harald, "New multimedia interface MHL market status and technology" 2012

      8 "Mobile-high-definition link specification, ver. 2.0"

      9 "Mobile MHL Transmitters" Lattice Semiconductor

      10 "High-definition multimedia interface specification, ver. 1.4b"

      11 A. Kobayashi, "DisplayPort ver. 1.2 overview" 2010

      12 P. Latha, "Color Space Converter"

      13 P. S. Sahni, "An equalizer with controllable transfer function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort receivers in 28-nm UTBB-FDSOI" 24 (24): 2803-2807, 2016

      14 P. K. Hanumolu, "A wide-tracking range clock and data recovery circuit" 43 (43): 425-439, 2006

      15 S. Kim, "A dual PFD phase rotating multi-phase PLL for 5 Gbps PCI express gen2 multi-lane serial link receiver in $0.13{\mu}m$ CMOS" 234-235, 2007

      16 C. -H. Park, "A Low-Noise, 900-MHz VCO in $0.6-{\mu}m$ CMOS" 34 (34): 586-591, 1999

      17 H. Kim, "A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology" 546-547, 2016

      18 "A DTV Profile for Uncompressed High Speed Digital Interfaces, CTA-861-G"

      19 C.-C. Ju, "A 4Kx2K @60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver" 2014

      20 Y.-B. Luo, "A 250 Mb/s-to-3.4 Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer" 190-191, 2009

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
      2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
      2010-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2009-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2007-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.42 0.13 0.35
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.3 0.29 0.308 0.03
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