시간평균 클럭을 이용한 고 해상도 주파수합성기 = A High Resolution Frequency Synthesizer using the Time Average Clock

다국어 초록 (Multilingual Abstract)

High speed electronic systems demand frequency synthesizer with high resolution, wide bandwidth and fast switching speed. Therefore, we use Flying-Adder which provides all kinds of digital frequency synthesizers based on the architecture. In some cases, there are some difficulties to generate wanted frequencies due to inherent jitter of the output frequency. However “Flying-Adder” architecture which is a frequency and phase synthesis technique that is based on a VCO of multiple delay stages, can eliminate jitter problem. Additionally using clock frequency(time-average-frequency clock), wider bandwidth by can be obtained resulting in high resolution.
The proposed frequency synthesizer solved the glitch problem in the existing one-path frequency synthesizer. Futhermore, the signal paths are linked in the manner of not only non-synchronized approach but also synchronized approach to solve the problem of timing from two-path. Thus, proposed frequency synthesizer can get optimum resolution when VCO operates at 165.25MHz, by adjusting values of the frequency which we want from FREQ control word. This leads to the better performance reducing output delay time up to 22% comparing to the existing two-path and decreasing gate count down to 13%. This frequency synthesizer is composed of FPGA and designed through RTL level using Xilinx software.

목차 (Table of Contents)

• I. 서 론 1
• II. 주파수합성기 개요 3
• 2.1 주파수합성기 구조 및 동작 3
• 2.2 All-Digital FA 주파수합성기 6
• 2.3 아날로그와 All Digital 방식 비교 8
• 2.4 주파수합성기 위상 잡음 10
• III. 시간평균 주파수합성기 개요 12
• 3.1 시간평균 주파수 클럭 12
• 3.2 시간평균 주파수의 누산기 14
• 3.3 고정 VCO 모드 15
• Ⅳ. FA 주파수합성기 18
• 4.1 기존 FA 주파수합성기 18
• 4.2 기존 FA 주파수합성기 문제 20
• Ⅴ. 제안한 FA 주파수합성기 25
• Ⅵ. 성능 평가 30
• Ⅶ. 결론 38
• 참고문헌 39