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      Foreground Digital Calibration for Split-Capacitor DAC in SAR ADC

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      https://www.riss.kr/link?id=A108454121

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      다국어 초록 (Multilingual Abstract)

      Split-capacitive digital-to-analog converter (CDAC) in successive-approximation-resistor (SAR) analogto- digital converter (ADC) suffers from the linearity degraded by the capacitor mismatch and by parasitic capacitances from the least-significant-bit (LSB) array. This paper proposes a foreground digital calibration scheme to compensate nonidealities of a split-CDAC. The linearity errors of a split-CDAC are estimated by switching logic based on the proposed digital calibration. Our proposed SAR ADC architecture uses 10.5-bit uncalibrated output to generate 10-bit calibrated output by adding error codes and by multiplying calibration factor. The behavioral simulation results of a 10.5-bit SAR ADC showed the DNL and the INL improved 0.31LSB and 1.27LSB, respectively. SNDR and SFDR were enhanced by 6.2dB and 13dB for each.
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      Split-capacitive digital-to-analog converter (CDAC) in successive-approximation-resistor (SAR) analogto- digital converter (ADC) suffers from the linearity degraded by the capacitor mismatch and by parasitic capacitances from the least-significant-bit...

      Split-capacitive digital-to-analog converter (CDAC) in successive-approximation-resistor (SAR) analogto- digital converter (ADC) suffers from the linearity degraded by the capacitor mismatch and by parasitic capacitances from the least-significant-bit (LSB) array. This paper proposes a foreground digital calibration scheme to compensate nonidealities of a split-CDAC. The linearity errors of a split-CDAC are estimated by switching logic based on the proposed digital calibration. Our proposed SAR ADC architecture uses 10.5-bit uncalibrated output to generate 10-bit calibrated output by adding error codes and by multiplying calibration factor. The behavioral simulation results of a 10.5-bit SAR ADC showed the DNL and the INL improved 0.31LSB and 1.27LSB, respectively. SNDR and SFDR were enhanced by 6.2dB and 13dB for each.

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      목차 (Table of Contents)

      • Abstract
      • I. 서론
      • II. Nonlinearity analysis
      • Ⅲ. Proposed calibration method
      • Ⅳ. 시뮬레이션 결과
      • Abstract
      • I. 서론
      • II. Nonlinearity analysis
      • Ⅲ. Proposed calibration method
      • Ⅳ. 시뮬레이션 결과
      • Ⅴ. 결론 및 향후 연구방향
      • 참고문헌
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