저전력 Single-Slope ADC를 사용한 CMOS 이미지 센서의 설계 = Design of a CMOS Image Sensor Based on a Low Power Single-Slope ADC

국문 초록 (Abstract)

모바일 기기에 장착되는 CMOS 이미지 센서(CIS) 칩은 배터리 용량의 한계로 인해 저전력 소모를 요구한다. 본 논문에서는 전력소모를 줄일 수 있는 데이터 플립플롭 회로와 새로운 저전력 구조의 Single-Slope A/D Converter(SS-ADC)를 사용한 이미지 센서를 설계하여 모바일 기기에 사용되는 CIS 칩의 전력 소모를 감소시켰다. 제안하는 CIS는 2.25㎛×2.25㎛ 면적을 갖는 4-Tr Active Pixel Sensor 구조를 사용하여 QVGA(320×240)급 해상도를 갖도록 설계되었으며 0.13㎛ CMOS 공정에서 설계되었다. 실험 결과, CIS 칩 내부의 SS-ADC 는 10-b 해상도를 가지며, 동작속도는 16 frame/s 를 만족하였고, 전원 전압 3.3V(아날로그)/1.8V(Digital)에서 25㎽의 전력 소모를 보였다. 측정결과로부터 제안된 CIS 칩은 기존 CIS 칩에 비해 대기시간동안 약 22%, 동작시간동안 약 20%의 전력이 감소되었다.

다국어 초록 (Multilingual Abstract)

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13㎛ CMOS process, the chip satisfies QVGA resolution(320×240 pixels) whose pitch is 2.25㎛ and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25㎽ at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

목차 (Table of Contents)

• 요약
• Abstract
• Ⅰ. 서론
• Ⅱ. CMOS 이미지 센서의 설계
• Ⅲ. 실험
• Ⅳ. 결론
• 참고문헌
• 저자소개

참고문헌 (Reference)

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