4 채널 36 Gb/s 27-1 초고속 의사 이진수열 (PRBS) 발생기의 집적화 설계 = Design of the Integrated 4-channel 36 Gb/s 27-1 PRBS Generator

다국어 초록 (Multilingual Abstract)

In this paper, a 36 Gb/s 27-1 Pseudo-Random Bit Sequence (PRBS) generator is implemented using a 0.13 μm SiGe process. In order to achieve four different 36 Gb/s PRBS patterns from the half-rate PRBS architecture, the output of the 6th latch in the interleaved linear feedback shift register (LFSR) is connected to the input of one XOR, and 0th, 2nd, 3rd, or 5th output of the FF in the LFSR is used to the input of the other XOR. We also implemented a 4×1 clock distribution circuit using three size-reduced Wilkinson power dividers with lumped-elements having the size of 380×380 μm2 to apply clock signals to the same magnitude and phase to four independent PRBS generators. Also, a trigger circuit was designed to verify the normal operation of the PRBS generator. The power consumption per the implemented PRBS generator is 282.5 mW from the 1.2V 및 2.5V power supply voltages, and the size of the individual PRBS generator is 0.5×0.23mm2.

국문 초록 (Abstract)

본 논문에서는 36 Gb/s급 27-1 Pseudo-Random Bit Sequence (PRBS) 신호발생기를 0.13μm SiGe 공정을 이용하여 구현하였다. 4 개의 서로 다른 36 Gb/s PRBS 패턴을 half-rate PRBS 구조에서 구현하기 위해 interleaved Linear Feedback Shit Register (LFSR)을 사용하여 6번째 latch의 출력은 항상 XOR의 입력단에 연결 하고 LFSR에서 0,2,3,5 번째 FF의 출력을 XOR의 다른 입력으로 사용하였다. 또한 4개의 독립적인 PRBS 신호발생기에 동일한 크기 및 위상을 가지는 4×1 clock 신호를 인가하기 위하여 Lumped-element를 사용하여 380×380 μm2 크기로 소형화된 3개의 Wilkinson 전력분배기를 이용하여 구현 하였다. 또한 PRBS 신호발생기의 정상동작을 검증하기 위해 trigger회로가 설계되었다. 구현된 PRBS 신호발생기당 전력소모는 1.2V 및 2.5V 전원전압으로부터 282.5 mW이고, 구현된 개별 PRBS 신호 발생기의 크기는 0.5×0.23 mm2이다.

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