Parallel PNP 및 N+ drift가 삽입된 높은홀딩전압특성을 갖는 ESD보호회로에 관한 연구 = A Study on ESD Protection Circuit with High Holding Voltage with Parallel PNP and N+ difrt inserted

다국어 초록 (Multilingual Abstract)

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changesof LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than theexisting LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-upimmunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width ofparasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device wereverified through Synopsys’ TCAD simulation so that it can be applied to the required application by applying theN-Stack technology.

국문 초록 (Abstract)

본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 구조적 변화를 통해 높은 홀딩전압 특성을 가지는 ESD 보호소자를제안한다. 제안된 ESD 보호소자는 병렬 PNP path와 긴 N+ drift 영역을 삽입하여 기존의 LVTSCR보다 높은 홀딩전압을 가지며, 일반적인 SCR 기반 ESD보호소자의 단점인 Latch-up 면역특성을 향상시킨다. 또한 기생 BJT들의 유효 베이스 폭을설계변수로 설정하였으며, N-Stack 기술을 적용하여 요구되는 application에 적용할 수 있도록 시놉시스사의 TCAD 시뮬레이션을 통해 제안된 ESD 보호소자의 전기적 특성을 검증하였다.

참고문헌 (Reference)

1 Z. Liu, "Silicon-Controlled Rectifier Stacking Structure for High-Voltage ESD Protection Applications" 31 (31): 845-847, 2010

2 M. D. Ker, "Overview of onchip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits" 5 (5): 235-249, 2005

3 Z. Wang, "Optimized pMOS-Triggered Bidirectional SCR for Low-Voltage ESD Protection Applications" 61 (61): 2588-2594, 2014

4 F. Ma, "High Holding Voltage SCR-LDMOS Stacking Structure With Ring-Resistance-Triggered Technique" 34 (34): 1178-1180, 2013

5 Y. C. Huang, "A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-um 5-V CMOS Process" 34 (34): 674-676, 2013