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      KCI등재 SCOPUS

      Control of Short-Channel Effects in Nano DG MOSFET Using Gaussian-Channel Doping Profile

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      https://www.riss.kr/link?id=A103576385

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      다국어 초록 (Multilingual Abstract)

      This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effectsin the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations werecompleted through a self-con...

      This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effectsin the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations werecompleted through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within thenon-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profileparameters such as the peak doping concentration and the straggle parameter were studied in terms of the draincurrent, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulationresults show that the short-channel effects were improved in correspondence with incremental changes of the straggleparameter and the peak doping concentration.

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      참고문헌 (Reference)

      1 H. Lu, 23 : 5006-, 2008

      2 M. Charmi, 24 : 047302-, 2015

      3 J. G. Fossum, 679-, 2003

      4 F. Venturi, 8 : 360-, 1989

      5 A. A. Ziabari, 51 : 844-, 2013

      6 Guohe Zhang, "Threshold Voltage Model of Short-Channel FD-SOI MOSFETs With Vertical Gaussian Profile" Institute of Electrical and Electronics Engineers (IEEE) 55 (55): 803-809, 2008

      7 Morteza Charmi, "The impact of high-k gate dielectric and FIBL on performance of nano DG-MOSFETs with underlapped source/drain regions" Springer Nature 13 (13): 307-312, 2014

      8 Jang-Gn Yun, "Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application" Elsevier BV 64 (64): 42-46, 2011

      9 R. Venugopal, "Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches" AIP Publishing 92 (92): 3730-, 2002

      10 Michele Goano, "Series expansion of the Fermi-Dirac integral over the entire domain of real j and x" Elsevier BV 36 (36): 217-221, 1993

      1 H. Lu, 23 : 5006-, 2008

      2 M. Charmi, 24 : 047302-, 2015

      3 J. G. Fossum, 679-, 2003

      4 F. Venturi, 8 : 360-, 1989

      5 A. A. Ziabari, 51 : 844-, 2013

      6 Guohe Zhang, "Threshold Voltage Model of Short-Channel FD-SOI MOSFETs With Vertical Gaussian Profile" Institute of Electrical and Electronics Engineers (IEEE) 55 (55): 803-809, 2008

      7 Morteza Charmi, "The impact of high-k gate dielectric and FIBL on performance of nano DG-MOSFETs with underlapped source/drain regions" Springer Nature 13 (13): 307-312, 2014

      8 Jang-Gn Yun, "Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application" Elsevier BV 64 (64): 42-46, 2011

      9 R. Venugopal, "Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches" AIP Publishing 92 (92): 3730-, 2002

      10 Michele Goano, "Series expansion of the Fermi-Dirac integral over the entire domain of real j and x" Elsevier BV 36 (36): 217-221, 1993

      11 Martin M. Frank, "Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)" Elsevier BV 86 (86): 1603-1608, 2009

      12 S. Datta, "Quantum Transport: Atom to Transistor" Cambridge University Press 2005

      13 Mincheol Shin, "Quantum Simulation of Device Characteristics of Silicon Nanowire FETs" Institute of Electrical and Electronics Engineers (IEEE) 6 (6): 230-237, 2007

      14 S. M. Sze, "Physics of Semiconductor Devices" 1983

      15 Khairul Alam, "Performance of 2 nm gate length carbon nanotube field-effect transistors with source∕drain underlaps" AIP Publishing 87 (87): 073104-, 2005

      16 Supriyo Datta, "Nanoscale device modeling: the Green’s function method" Elsevier BV 28 (28): 253-278, 2000

      17 M. Lundstrom, "Nanoscale Transistors: Device Physics Modeling and Simulation" Springer Press 2006

      18 "International Technology Roadmap for Semiconductor"

      19 M. Lundstrom, "Essential physics of carrier transport in nanoscale MOSFETs" Institute of Electrical and Electronics Engineers (IEEE) 49 (49): 133-141, 2002

      20 Sishir Bhowmick, "Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors" Springer Nature 2 (2): 83-88, 2010

      21 Morteza Charmi, "Design considerations of underlapped source/drain regions with the Gaussian doping profile in nano-double-gate MOSFETs: A quantum simulation" Elsevier BV 16 (16): 311-317, 2013

      22 Ali A. Orouji, "Design considerations of source and drain regions in nano double gate MOSFETs" Elsevier BV 15 (15): 572-577, 2012

      23 Antonio Cerdeira, "Compact model for short channel symmetric doped double-gate MOSFETs" Elsevier BV 52 (52): 1064-1070, 2008

      24 Lining Zhang, "Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect" Elsevier BV 50 (50): 1062-1070, 2010

      25 Lining Zhang, "Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET" Elsevier BV 54 (54): 806-808, 2010

      26 Kunihiro Suzuki, "Analytical Model for Redistribution Profile of Ion-Implanted Impurities During Solid-Phase Epitaxy" Institute of Electrical and Electronics Engineers (IEEE) 54 (54): 262-271, 2007

      27 S. Karmalkar, "A process-parameter-based circuit simulation model for ion-implanted MOSFETs and MESFETs" Institute of Electrical and Electronics Engineers (IEEE) 24 (24): 139-145, 1989

      28 Feng Liu, "A Non-Charge-Sheet Analytic Model for Symmetric Double-Gate MOSFETs With Smooth Transition Between Partially and Fully Depleted Operation Modes" Institute of Electrical and Electronics Engineers (IEEE) 55 (55): 3494-3502, 2008

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      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2011-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2009-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2006-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2005-05-30 학회명변경 영문명 : 미등록 -> The Korean Institute of Electrical and Electronic Material Engineers KCI등재후보
      2005-05-30 학술지명변경 한글명 : Transactions on Electrical and Electroni -> Transactions on Electrical and Electronic Materials KCI등재후보
      2005-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2003-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.08 0.08 0.1
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