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      KCI등재 SCIE SCOPUS

      Influence of Parasitic Parameters on Switching Characteristics and Layout Design Considerations of SiC MOSFETs

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      https://www.riss.kr/link?id=A105455084

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      다국어 초록 (Multilingual Abstract)

      Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.
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      Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combin...

      Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

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      참고문헌 (Reference)

      1 S. Clemente, "Understanding HEXFET switching performance" International Rectifier, Inc. 2013

      2 J. Wang, "The latest technology research and application prospects of the intelligent electrical apparatus" 30 (30): 1-11, 2015

      3 "The influence of parasitic network parameters on the switching behavior of power MOSFETs when switching ohmic/inductive loads"

      4 Y. Zheng, "The SiC age of power electronics is coming towards us" 5 (5): 1-2, 2006

      5 A. Anthon, "Switching investigations on a SiC MOSFET in a TO-247 package" 1 : 1854-1860, 2014

      6 P. Nayak, "Study of the effects of parasitic inductances and device capacitances on 1200 V, 35A SiC MOSFET based voltage source inverter design" 1 : 1-6, 2014

      7 Z. Qian, "Progress in power electronics system integration" 3 (3): 2-14, 2006

      8 M. Liang, "Performance comparison of SiC MOSFET, Si CoolMOS, and IGBT for DAB converter" 12 (12): 41-50, 2015

      9 Z. Dong, "Impact of common source inductance on switching loss of SiC MOSFET" 1 : 1-5, 2015

      10 B. Cougo, "High current ripple for power density and efficiency improvement in wide bandgap transistor-based buck converters" 30 (30): 4489-4504, 2015

      1 S. Clemente, "Understanding HEXFET switching performance" International Rectifier, Inc. 2013

      2 J. Wang, "The latest technology research and application prospects of the intelligent electrical apparatus" 30 (30): 1-11, 2015

      3 "The influence of parasitic network parameters on the switching behavior of power MOSFETs when switching ohmic/inductive loads"

      4 Y. Zheng, "The SiC age of power electronics is coming towards us" 5 (5): 1-2, 2006

      5 A. Anthon, "Switching investigations on a SiC MOSFET in a TO-247 package" 1 : 1854-1860, 2014

      6 P. Nayak, "Study of the effects of parasitic inductances and device capacitances on 1200 V, 35A SiC MOSFET based voltage source inverter design" 1 : 1-6, 2014

      7 Z. Qian, "Progress in power electronics system integration" 3 (3): 2-14, 2006

      8 M. Liang, "Performance comparison of SiC MOSFET, Si CoolMOS, and IGBT for DAB converter" 12 (12): 41-50, 2015

      9 Z. Dong, "Impact of common source inductance on switching loss of SiC MOSFET" 1 : 1-5, 2015

      10 B. Cougo, "High current ripple for power density and efficiency improvement in wide bandgap transistor-based buck converters" 30 (30): 4489-4504, 2015

      11 Z. Chen, "Experimental parametric study of the parasitic inductance influence on MOSFET switching characteristics" 1 : 164-169, 2010

      12 H. Li, "Detail study of SiC MOSFET switching characteristics" 1 : 1-5, 2014

      13 J. Wang, "Characterization and experimental assessment of the effects of parasitic elements on the MOSFET switching performance" 28 (28): 573-590, 2013

      14 J. Wang, "Characterization and experimental assessment of the effects of parasitic elements on the MOSFET switching performance" 28 (28): 573-590, 2013

      15 Z. Wang, "Analysis of stray inductance's influence on SiC MOSFET switching performance" 1 : 2838-2843, 2014

      16 J. Noppakunkajorn, "Analysis of high-Speed PCB with SiC devices by investigating turn-Off overvoltage and interconnection inductance influence" 1 (1): 118-125, 2015

      17 "Advanced power semiconductor devices- challenges and solutions in applications"

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-10-08 학술지명변경 한글명 : 전력전자학회 영문논문지 -> Journal of Power Electronics KCI등재
      2010-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2007-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2006-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2004-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.83 0.54 0.74
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.65 0.62 0.382 0.06
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