1 J. Jang, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory" IEEE International 192-193, 2009
2 J.-G. Yun, "Single-crystalline Si STacked ARray (STAR) NAND flash memory" 59 (59): 35-45, 2012
3 "Sentaurus Device User Guide, Version J-2014.9"
4 W. S. Cho, "Reliable Vertical NAND Technology with Biconcave Shaped Storage Layer and Leakage Controllable Offset Structure" IEEE International 130-131, 2010
5 R. Katsumata, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices" IEEE International 136-137, 2009
6 S. Aritome, "NAND Flash Memory Technologies" Wiley-IEEE Press 21-36, 2015
7 W. Kim, "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" IEEE International 188-189, 2009
8 E.-S. Choi, "Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in Near Future" 9.4.1-9.4.4, 2012
9 J. Yanagihara, "Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory" 20-23, 2012
10 H. Tanaka, "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory" IEEE International 14-15, 2007
1 J. Jang, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory" IEEE International 192-193, 2009
2 J.-G. Yun, "Single-crystalline Si STacked ARray (STAR) NAND flash memory" 59 (59): 35-45, 2012
3 "Sentaurus Device User Guide, Version J-2014.9"
4 W. S. Cho, "Reliable Vertical NAND Technology with Biconcave Shaped Storage Layer and Leakage Controllable Offset Structure" IEEE International 130-131, 2010
5 R. Katsumata, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices" IEEE International 136-137, 2009
6 S. Aritome, "NAND Flash Memory Technologies" Wiley-IEEE Press 21-36, 2015
7 W. Kim, "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" IEEE International 188-189, 2009
8 E.-S. Choi, "Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in Near Future" 9.4.1-9.4.4, 2012
9 J. Yanagihara, "Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory" 20-23, 2012
10 H. Tanaka, "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory" IEEE International 14-15, 2007