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      KCI등재 SCIE SCOPUS

      Vertical Channel NAND Flash Structure using DSCG(Double-Side-Control-Gate) to Reduce Cell to Cell Interference

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      https://www.riss.kr/link?id=A105951920

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      다국어 초록 (Multilingual Abstract)

      In this study we proposed the ‘Double-Side-Control-Gate’(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was...

      In this study we proposed the ‘Double-Side-Control-Gate’(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the reduction of interference effect. To demonstrate the performance improvement of the proposed architecture, we analyzed cell-to-cell interference in 3- bit multi-cells and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared and estimated benefits expected from the application of DSCG by calculating Cell-to-Cell Distance(CTCD), pass voltage, etc. Lastly, we confirmed the above 90% reduction of the Cell-to- Cell interference using the DSCG structure.

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      목차 (Table of Contents)

      • Abstract
      • I. INTRODUCTION
      • II. ARCHITECTURE
      • III. SIMULATION RESULTS AND DISCUSSIONS OF INTERFERENCE EFFECT
      • V. CONCLUSIONS
      • Abstract
      • I. INTRODUCTION
      • II. ARCHITECTURE
      • III. SIMULATION RESULTS AND DISCUSSIONS OF INTERFERENCE EFFECT
      • V. CONCLUSIONS
      • REFERENCES
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      참고문헌 (Reference)

      1 J. Jang, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory" IEEE International 192-193, 2009

      2 J.-G. Yun, "Single-crystalline Si STacked ARray (STAR) NAND flash memory" 59 (59): 35-45, 2012

      3 "Sentaurus Device User Guide, Version J-2014.9"

      4 W. S. Cho, "Reliable Vertical NAND Technology with Biconcave Shaped Storage Layer and Leakage Controllable Offset Structure" IEEE International 130-131, 2010

      5 R. Katsumata, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices" IEEE International 136-137, 2009

      6 S. Aritome, "NAND Flash Memory Technologies" Wiley-IEEE Press 21-36, 2015

      7 W. Kim, "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" IEEE International 188-189, 2009

      8 E.-S. Choi, "Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in Near Future" 9.4.1-9.4.4, 2012

      9 J. Yanagihara, "Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory" 20-23, 2012

      10 H. Tanaka, "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory" IEEE International 14-15, 2007

      1 J. Jang, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory" IEEE International 192-193, 2009

      2 J.-G. Yun, "Single-crystalline Si STacked ARray (STAR) NAND flash memory" 59 (59): 35-45, 2012

      3 "Sentaurus Device User Guide, Version J-2014.9"

      4 W. S. Cho, "Reliable Vertical NAND Technology with Biconcave Shaped Storage Layer and Leakage Controllable Offset Structure" IEEE International 130-131, 2010

      5 R. Katsumata, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices" IEEE International 136-137, 2009

      6 S. Aritome, "NAND Flash Memory Technologies" Wiley-IEEE Press 21-36, 2015

      7 W. Kim, "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" IEEE International 188-189, 2009

      8 E.-S. Choi, "Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in Near Future" 9.4.1-9.4.4, 2012

      9 J. Yanagihara, "Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory" 20-23, 2012

      10 H. Tanaka, "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory" IEEE International 14-15, 2007

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
      2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
      2010-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2009-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2007-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.42 0.13 0.35
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.3 0.29 0.308 0.03
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