높은 선형성을 갖는 새로운 구조의 MMIC 저잡음 증폭기

국문 초록 (Abstract)

본 논문에서는 캐스코드(cascode) 구조에 트랜지스터를 추가하여 잡음 특성을 유지하면서 높은 선형성을 갖는 저잡음 증폭기 구조를 제안하고 설계하였다. 제안한 구조는 트랜지스터의 사이즈 최적화를 통해 잡음원을 최소화 했으며, 전류원분리(current bleeding) 효과를 주어 선형성을 개선하였다. 저잡음 특성에 유리한 0.5 μm pHEMT 공정을 이용해 제작된 저잡음 증폭기는 1.8～2.6 GHz의 동작 대역에서 30.8 dBm의 OIP3, 15.0 dB의 이득, 1.1 dB의 NF, 11.6 dB/10.4 dB의 입출력반사 손실 특성을 보였다.

다국어 초록 (Multilingual Abstract)

This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a 0.5 μm GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an OIP3 of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.

목차 (Table of Contents)

• 요약
• Abstract
• Ⅰ. 서론
• Ⅱ. 저잡음 증폭기의 설계 및 측정
• Ⅲ. 결론
• References

참고문헌 (Reference)

1 Jingshi Yao, "Ultra lownoise highly linear integrated 1.5 to 2.7 GHz LNA" 1-4, 2014

2 S. Kumar, "Enhancement mode GaAs pHEMT LNA with linearity control and phased matched mitigated bypass switch and differential active mixer" 3 : 1577-1580, 2003

3 B. Prameela, "Design of a MESFET based low noise amplifier with improved noise figure for low power wireless applications in 2~3 GHz" 257-260, 2013

4 T. K. Nguyen, "A power constrained simultaneous noise and input matched low noise amplifier design technique" 4 : 23-26, 2004

5 A. Fazal, "A novel cascode feedback GaAs MMIC LNA with transformer-coupled output using multiple fabrication processes" 2 (2): 70-72, 1992

6 B. Kim, "A new linearization technique for MOSFET RF amplifier using multiple gated transistor" 10 (10): 371-373, 2000

7 S. Ock, "A modified cascode type low noise amplifier using dual common source transistors" 3 : 1423-1426, 2002