1 최병길, "이상적인 이중-게이트 벌크 FinFET의 전기적 특성고찰" 대한전자공학회 43 (43): 1-7, 2006
2 Dambrine, "what are the limiting parameters of deep submicron MOSFETs for high frequency applications" 24 (24): 189-191, 2003
3 "The International Technology Roadmap for Semiconductors(ITRS)"
4 "Synopsys Sentaurus Device User Guide Ver.E-2010.12"
5 조성재, "Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters" 대한전자공학회 10 (10): 265-275, 2010
6 L. Wei, "Parasitic Capacitance : Analytical Models and Impact on Circuit-Level Performance" 58 (58): 1361-1370, 2011
7 W. Yang, "On the feasibility of nanoscale triple gate CMOS transistors" 52 (52): 1159-1164, 2005
8 J. Kedzierski, "Fabrication of metal-gated FinFETs through complete gate silicidation with Ni" 51 (51): 2115-2120, 2004
9 D. Lederer, "Dependence of finFET RF performance on fin width" 4-6, 2006
10 K. W. Lee, "Comparative study of analog performance of multiple fin tri-gate FinFETs" 2012
1 최병길, "이상적인 이중-게이트 벌크 FinFET의 전기적 특성고찰" 대한전자공학회 43 (43): 1-7, 2006
2 Dambrine, "what are the limiting parameters of deep submicron MOSFETs for high frequency applications" 24 (24): 189-191, 2003
3 "The International Technology Roadmap for Semiconductors(ITRS)"
4 "Synopsys Sentaurus Device User Guide Ver.E-2010.12"
5 조성재, "Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters" 대한전자공학회 10 (10): 265-275, 2010
6 L. Wei, "Parasitic Capacitance : Analytical Models and Impact on Circuit-Level Performance" 58 (58): 1361-1370, 2011
7 W. Yang, "On the feasibility of nanoscale triple gate CMOS transistors" 52 (52): 1159-1164, 2005
8 J. Kedzierski, "Fabrication of metal-gated FinFETs through complete gate silicidation with Ni" 51 (51): 2115-2120, 2004
9 D. Lederer, "Dependence of finFET RF performance on fin width" 4-6, 2006
10 K. W. Lee, "Comparative study of analog performance of multiple fin tri-gate FinFETs" 2012
11 H. Lee, "Characterization issues of gate geometry in multifinger structure for RF-SOI MOSFETs" 23 (23): 288-290, 2002
12 A. Dixit, "Analysis of the parasitic S/D resistance in multiple-gate FETs" 52 (52): 1132-1140, 2005
13 H. Zhao, "Analysis of the effects of fringing electric field on FinFET device performance and structural optimization using 3-D simulation" 55 (55): 1177-1184, 2008
14 Balasubramanian Murugan, "Analysis of Subthreshold Behavior of FinFET using Taurus" 7 (7): 2007