Study on the Performance Evaluation and Analysis of Mobile Cache Memory

다국어 초록 (Multilingual Abstract)

In this paper, we analyze the characteristics of mobile cache, which is used to improve the data access speed when executing applications on mobile devices, and verify the importance of mobile cache through a cache data access experiment. The mobile device market has grown at a fast pace over the past decade; however, battery limitations and size, price considerations restrict the usage of fast hardware. Thus, their performance are supplemented by using a memory buffer structure such as the cache memory. The analysis mainly focuses on cache size, hierarchical structure of cache, cache replacement policy, and the effect these features has on mobile performance. For the experimental data, we applied a data set from a microprocessor system study, originally used to test the cache performance. In the experimental results, the average data access speed on a mobile device showed a performance improvement of up to 10 times with the presence of cache memory than without. Accordingly, the cache memory was helpful for the performance improvement of a mobile device when the specifications were identical.

참고문헌 (Reference)

1 문현주, "캐시 주소의 태그 이력을 활용한 에너지 효율적 고성능 데이터 캐시 구조" 한국정보처리학회 14 (14): 55-62, 2007

2 "Wikipedia"

3 "WikiChip"

4 H. Kim, "What is a good buffer cache replacement scheme for mobile flash storage?" (12) : 235-246, 2012

5 M. D. Lam, "The cache perfor mance and optimizations of blocked algorithms" Association for Computing Machinery (5) : 63-74, 1991

6 H. Al-Zoubi, "Performance evaluation of cache replacement policies for the SPEC CPU2000benchmark suite" Association for Computing Machinery (42) : 267-272, 2004

7 "Passmark"

8 J. L. Baer, "On the inclusion properties for multi-level cache hierarchies" Association for Computing Machinery (98) : 345-352, 1998

9 J. Ahmed, "Multiprocessors and Cache Memory" 2017

10 S. Jiang, "LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache perfor mance" (2) : 31-42, 2002

11 Wicker, "L2-Cache-Simulator"

12 J. E. Smith, "Instruction Cache Replacement Policies and Organizations" Institute of Electrical and Electronics Engineers (IEEE) C-34 (C-34): 234-241, 1985

13 Y. Kim, "Impact of processor cache memory on storage performance" Institute of Electrical and Electronics Engineers Inc 304-305, 2017

14 A. Gutierrez, "Full-system analysis and character ization of interactive smartphone applications" (11) : 81-90, 2011

15 H. Mehboob, "ENHANCE THE PERFORMAN CE OF ASSOCIATIVE MEMORY BY USING NEW METHOD S" 12 (12): 49-56, 2017

16 S. Przybylski, "Characteristics of performance-optimal multi-level cache hierarchies" Associatio n for Computing Machinery (89) : 114-121, 1989

17 A. Asaduzzaman, "Cache optimization for mobile devices running multimedia applications" (4) : 499-506, 2004

18 Alan Jay Smith, "Cache Memories" Association for Computing Machinery (ACM) 14 (14): 473-530, 1982

19 S. Park, "CFLRU : a replacement algorithm for flash memory" (8) : 234-241, 2006

20 Wikipedia, "Apple A12X Processor"

21 P. Panda, "A survey on replacement strategies in cache memory for embedded systems" 12-17, 2016

22 Tae-Young Oh, "A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation" Institute of Electrical and Electronics Engineers (IEEE) 50 (50): 178-190, 2015

23 T. Johnson, "2Q : A Low Overhead High Performance Buffer Management Replacement Algorithm" Morgan Kaufmann Publishers Inc 94 (94): 439-450, 1994