A Low Power Design of H.264 Codec Based on Hardware and Software Co-design

다국어 초록 (Multilingual Abstract)

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-Core Platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720×480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400㎒@30fps with CIF(Common Intermediated Format) and about 100k per core for H.264 decoder.

목차 (Table of Contents)

• Abstracts
• Ⅰ. Introduction
• Ⅱ. Design of Parameters for H.264 Encoder
• Ⅲ. Design of Architecture for H.264 Encoder
• Ⅳ. Design of Application Specific Processor
• Ⅴ. Verification for hardware and software Platform
• Ⅵ. Conclusions
• References
• 약력