This paper reports an injection‐locked frequency divider (ILFD) with a divide‐by‐five feature, a built‐in balun, and low power consumption fabricated in a standard 0.18 μm CMOS process. By employing a fourth harmonic (4f0) enhancement techn...
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https://www.riss.kr/link?id=O111880115
2021년
-
0895-2477
1098-2760
SCIE;SCOPUS
학술저널
64-68 [※수록면이 p5 이하이면, Review, Columns, Editor's Note, Abstract 등일 경우가 있습니다.]
0
상세조회0
다운로드다국어 초록 (Multilingual Abstract)
This paper reports an injection‐locked frequency divider (ILFD) with a divide‐by‐five feature, a built‐in balun, and low power consumption fabricated in a standard 0.18 μm CMOS process. By employing a fourth harmonic (4f0) enhancement techn...
This paper reports an injection‐locked frequency divider (ILFD) with a divide‐by‐five feature, a built‐in balun, and low power consumption fabricated in a standard 0.18 μm CMOS process. By employing a fourth harmonic (4f0) enhancement technique realized in a stacked cross‐coupled pair and mixing with an injection signal (5f0) through injection transistors, an output signal (f0 = 5f0‐4f0) is obtained without using extra passive devices. The built‐in balun is employed to transfer a single‐ended signal to differential signals injected into injection transistors. The proposed ILFD improves the locking range without the help of varactors and the power dissipation by adopting two cross‐coupled transistor pairs. The proposed ILFD has the free‐running frequency of 4.3 GHz and the injection frequencies from 21.1 to 22.1 GHz at an input power level of 0 dBm. The proposed ILFD core only consumes 3.75 mW from a supply voltage of 1.5 V.
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