Proposal of a small logic block for a reconfigurable device with flexibility on mapping of routing and logic cell

다국어 초록 (Multilingual Abstract)

A memory based PLD (MPLD) has been proposed as one of reconfigurable device. A MPLD consists of multiple-output look-up tables (MLUTs) which is reconfigurable element diagonally connected by AD pairs. MPLD can improve routing ability among logic elements by increasing the number of AD pairs. However, there is problem that chip area of MLUT will be doubled by each additional AD pairs. On the other hand, if a MLUT with fewer number of AD pairs is used for small chip area, it decreases logic density since many MLUTs are used as a part of routing resources. To solve the problem, we propose a small logic element while keeping routing ability high, compared with MLUT. We adopted selector-based logic element to decrease chip area. From the estimation results in this paper, we found that the number of transistor counts required to implement our proposed logic element is decreased to 18.7 % of transistor counts, compared with MLUT with six AD pairs.

목차 (Table of Contents)

• Abstract
• 1. Introduction
• 2. Proposal of selector-based PLD
• 3. Evaluation
• 4. Conclusion
• References