패턴 공유를 이용한 게이트 지연 고장 검사 패턴의 생성 = Test Pattern Genetation for Gate Delay Faluts by Sharing Test Patterns

다국어 초록 (Multilingual Abstract)

Delay testing becomes very important as the complexity and the performance of the VLSI increase. Since test generation is cpu-intensive process, various ways to improve the test generation speed have been proposed and tried regardless the types of fault model. This paper presents a simple and efficient method for accelerating test pattern generation process for gate delay faults in combinational circuits. We implemented several delay test pattern generators and ran on ISCAS-85 benchmark circuits. The result showed improved performance in test pattern generation for gate delay faults.