분할 전류원을 이용한 Wide Dynamic Range 저전력 Single-Slope ADC

다국어 초록 (Multilingual Abstract)

This paper describes a low power technique for a single-slope ADC with a wide dynamic range (DR). The proposed technique is implemented to a singleslope ADC architecture to optimize the power consumption of a system with an enhanced DR performance. To improve the power efficiency of a single-slope ADC with an enhanced DR, an adaptive split current source is proposed in the comparator of the single-slope ADC. The bias current of the comparator is split based on the minimum-tomaximum DR ratio of the ADC. The aim of split current source is to adaptively control the bias current depending on the input DR. By utilizing the modified architecture of the comparator, the singleslope ADC is able to optimize the power consumption depending on the target DR with minimum loss of performance. The proposed low power technique is designed and simulated in a 28 nm CMOS process. The simulation results of the single-slope ADC containing a split current source architecture shows that the power consumption of the single-slope ADC is saved by 30% with a 1:2 output ratio, which is a remarkable outcome from a simple modification.