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https://www.riss.kr/link?id=O106936762
2018년
eng
학술저널
Symposium on integrated circuits and systems design
260-265 [※수록면이 p5 이하이면, Review, Columns, Editor's Note, Abstract 등일 경우가 있습니다.]
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI 2018)
Bento Goncalves, Brazil
2018; Aug
0
상세조회0
다운로드
TESTABLE ERROR DETECTION LOGIC DESIGN APPLIED TO AN ASYNCHRONOUS TIMING RESILIENT TEMPLATE
EXTRACTING PACKET DEPENDENCE FROM NOC SIMULATION TRACES USING ASSOCIATION RULE MINING
EVALUATION OF COMPILER OPTIMIZATION FLAGS EFFECTS ON SOFT ERROR RESILIENCY
16NM 6T AND 8T CMOS SRAM CELL ROBUSTNESS AGAINST PROCESS VARIABILITY AND AGING EFFECTS