저 전압 스윙 기술과 슬립 트랜지스터를 이용한 저 전력 전류모드 논리 곱셈기 설계 = Design of a Low-Power MOS Current Mode Logic Multiplier Using Low-Swing Technology and Sleep Transistor

다국어 초록 (Multilingual Abstract)

This paper proposes a low-power MOS current-mode logic multiplier using low-swing technology and sleep transistor. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ㎛ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.