As the (7,3) cyclic code is applied to the design of the counter, unit block is a three-bit count module with four redundant bits. Thus the proposed implementation is an approach for realizing the modular LSI of sequential circuit with high informatio...
As the (7,3) cyclic code is applied to the design of the counter, unit block is a three-bit count module with four redundant bits. Thus the proposed implementation is an approach for realizing the modular LSI of sequential circuit with high information rate. More than three-bit circuit realization is attainable by connecting three-bit count modules in cascade.
In this paper, a synthesis procedure for realizing a single-failure-tolerant parallel binary counter with double-failure-detecting scheme is presented. Using the orthogonizable (7,3) cyclic code, double-failure-detecting count logic is accomplished in addition to single-failure-tolerant count logic.
The proposed techniques can be applied in principle to other sequential circuits to increase its reliability.