1 S. Deutsch, "Uncertainty-Aware Robust Optimization of Test-Access Architectures for 3D Stacked ICs" 1-10, 2013
2 L.-T. Wang, "Ultrascan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for Test Cost Reduction" 946-953, 2005
3 M. A. Ansari, "Time-Multiplexed Test Access Architecture for Stacked Integrated Circuits" 13 (13): 1-6, 2016
4 M. A. Ansari, "Time-Multiplexed 1687-Network for Test Cost Reduction"
5 J. M. Nolen, "Time-Division-Multiplexed Test Delivery for NoC Systems" 25 (25): 44-51, 2008
6 F. Vartziotis, "Time-Division Multiplexing for Testing DVFS-based SoCs" 34 (34): 668-681, 2015
7 B. Noia, "Test-Architecture Optimization for TSV-Based 3D Stacked ICs" 24-29, 2010
8 B. Noia, "Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs" 30 (30): 1705-1718, 2011
9 L. Jiang, "Test Architecture Design and Optimization for Three-Dimensional SoCs" 220-225, 2009
10 M. Agrawal, "Reuse-Based Optimization for Prebond and Postbond Testing of 3-D-Stacked ICs" 34 (34): 122-135, 2015
1 S. Deutsch, "Uncertainty-Aware Robust Optimization of Test-Access Architectures for 3D Stacked ICs" 1-10, 2013
2 L.-T. Wang, "Ultrascan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for Test Cost Reduction" 946-953, 2005
3 M. A. Ansari, "Time-Multiplexed Test Access Architecture for Stacked Integrated Circuits" 13 (13): 1-6, 2016
4 M. A. Ansari, "Time-Multiplexed 1687-Network for Test Cost Reduction"
5 J. M. Nolen, "Time-Division-Multiplexed Test Delivery for NoC Systems" 25 (25): 44-51, 2008
6 F. Vartziotis, "Time-Division Multiplexing for Testing DVFS-based SoCs" 34 (34): 668-681, 2015
7 B. Noia, "Test-Architecture Optimization for TSV-Based 3D Stacked ICs" 24-29, 2010
8 B. Noia, "Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs" 30 (30): 1705-1718, 2011
9 L. Jiang, "Test Architecture Design and Optimization for Three-Dimensional SoCs" 220-225, 2009
10 M. Agrawal, "Reuse-Based Optimization for Prebond and Postbond Testing of 3-D-Stacked ICs" 34 (34): 122-135, 2015
11 G. H. Loh, "Processor Design in 3D Die-Stacking Technologies" 27 (27): 31-48, 2007
12 B. Noia, "Optimization methods for post-bond testing of 3D stacked ICs" 28 (28): 103-120, 2012
13 S. Wang, "Multicast Testing of Interposer-Based 2. 5D IC s : Test-Architecture Design and Test Scheduling" 23 (23): 1-25, 2018
14 L. Jiang, "Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint" 191-196, 2009
15 "IEEE 3D-Test P1838 Working Group"
16 H. Vranken, "Enhanced Reduced Pin-Count Test for Full-Scan Design" 18 : 129-143, 2002
17 Y. Xie, "Design Space Exploration for 3D Architectures" 2 (2): 65-103, 2006
18 W. R. Davis, "Demystifying 3D ICs : The Pros and Cons of Going Vertical" 22 (22): 498-510, 2005
19 E. J. Marinissen, "Challenges and Emerging Solutions in Testing TSV-Based 2. 5D-and 3DStacked ICs" 2 : 1277-1282, 2012
20 C.-C. Yang, "A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs" 7-12, 2013
21 E. J. Marinissen, "A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs" 269-274, 2010
22 E. J. Marinissen, "A Set of Benchmarks for Modular Testing of SOCs" 519-528, 2002