RISS 학술연구정보서비스

검색
다국어 입력

http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.

변환된 중국어를 복사하여 사용하시면 됩니다.

예시)
  • 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
  • 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
닫기
    인기검색어 순위 펼치기

    RISS 인기검색어

      테스터블 PLA회로를 구현하기 위한 분할 방법과 설계기법

      한글로보기

      https://www.riss.kr/link?id=A89501474

      • 0

        상세조회
      • 0

        다운로드
      서지정보 열기
      • 내보내기
      • 내책장담기
      • 공유하기
      • 오류접수

      부가정보

      다국어 초록 (Multilingual Abstract)

      In this paper, we present an efficient pseudo exhaustive testable(PET) PLA(Programmable Logic Arrays)algorithm with extra lines inserted into input and output lines of the PLA`s. At testing the proposed extra line method uses extra input and output lines in addition to the given input and output lines of the PLA. The extra input lines are inserted in an AND plane and the extra output lines are inserted in an OR plane. By connecting an intersection between the product and extra lines, these inserted lines make the product line, and they are satisfied to the partitioning rules. The propsed algorithm results in fewer of total groups in an AND plane so that the number of test pattern hardware overhead and test time required are reduced.
      번역하기

      In this paper, we present an efficient pseudo exhaustive testable(PET) PLA(Programmable Logic Arrays)algorithm with extra lines inserted into input and output lines of the PLA`s. At testing the proposed extra line method uses extra input and output li...

      In this paper, we present an efficient pseudo exhaustive testable(PET) PLA(Programmable Logic Arrays)algorithm with extra lines inserted into input and output lines of the PLA`s. At testing the proposed extra line method uses extra input and output lines in addition to the given input and output lines of the PLA. The extra input lines are inserted in an AND plane and the extra output lines are inserted in an OR plane. By connecting an intersection between the product and extra lines, these inserted lines make the product line, and they are satisfied to the partitioning rules. The propsed algorithm results in fewer of total groups in an AND plane so that the number of test pattern hardware overhead and test time required are reduced.

      더보기

      동일학술지(권/호) 다른 논문

      동일학술지 더보기

      더보기

      분석정보

      View

      상세정보조회

      0

      Usage

      원문다운로드

      0

      대출신청

      0

      복사신청

      0

      EDDS신청

      0

      동일 주제 내 활용도 TOP

      더보기

      주제

      연도별 연구동향

      연도별 활용동향

      연관논문

      연구자 네트워크맵

      공동연구자 (7)

      유사연구자 (20) 활용도상위20명

      이 자료와 함께 이용한 RISS 자료

      나만을 위한 추천자료

      해외이동버튼