In this paper, we present an efficient pseudo exhaustive testable(PET) PLA(Programmable Logic Arrays)algorithm with extra lines inserted into input and output lines of the PLA`s. At testing the proposed extra line method uses extra input and output li...
In this paper, we present an efficient pseudo exhaustive testable(PET) PLA(Programmable Logic Arrays)algorithm with extra lines inserted into input and output lines of the PLA`s. At testing the proposed extra line method uses extra input and output lines in addition to the given input and output lines of the PLA. The extra input lines are inserted in an AND plane and the extra output lines are inserted in an OR plane. By connecting an intersection between the product and extra lines, these inserted lines make the product line, and they are satisfied to the partitioning rules. The propsed algorithm results in fewer of total groups in an AND plane so that the number of test pattern hardware overhead and test time required are reduced.