ADC-Based Backplane Receivers

다국어 초록 (Multilingual Abstract)

The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

목차 (Table of Contents)

• Abstract
• I. INTRODUCTION
• II. ADC-BASED RECEIVER ARCHITECTURE
• III. FRONT-END ADC
• IV. DIGITAL EQUALIZER
• V. SYSTEM-LEVEL OPTIMIZATION
• VI. CONCLUSION
• REFERENCES