A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-µm CMOS

다국어 초록 (Multilingual Abstract)

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65 %. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-μm CMOS, the PLL covers 154 ~ 303 MHz (VHF-III), 462 ~ 911 MHz (UHF), and 1441 ~ 1887 MHz (L1, L2) with two VCO’s while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

목차 (Table of Contents)

• Abstract
• Ⅰ. INTRODUCTION
• Ⅱ. ARCHITECTURE
• Ⅲ. BUILDING BLOCK DESIGN
• Ⅳ. MEASUREMENT RESULTS
• Ⅴ. CONCLUSIONS
• ACKNOWLEDGMENTS
• REFERENCES