Spin Hall Effect-based Nonvolatile Flip Flop for Fine-grained Power Gating

다국어 초록 (Multilingual Abstract)

This paper presents a nonvolatile flip flop (NVFF) for fine-grained power gating with data retention. The proposed NVFF exploits the spin Hall effect (SHE) for low-power and highspeed data backup operations. In order to evaluate the performance of the proposed NVFF, a simulation framework was used that consists of a SPICE circuit simulator and a Landau-Lifshitz-Gilbert solver. This work investigates the effect of process variation on the backup-and-restore operations, and shows that the proposed NVFF can achieve <5ns backup and <2ns restore operations even under process variations in the transistor and spin Hall device. Compared to the conventional spin transfer torque–based NVFF, the proposed NVFF improves the break-even time by more than three times because of the high spin injection efficiency of SHE and the simple single-phase backup mechanism.

목차 (Table of Contents)

• Abstract
• 1. Introduction
• 2. Spin Hall Effect.based NVFF
• 3. Simulation and Results
• 4. Conclusion
• References

참고문헌 (Reference)

1 L. Liu, "Spin-torque switching with the giant spin Hall effect of tantalum" 336 (336): 2012

2 W. Zhao, "Spin-MTJ based Non-Volatile Flip-Flop" 399-402, 2007

3 C. F. Pai, "Spin transfer torque devices utilizing the giant spin Hall effect of tungsten" 101 : 122404-, 2012

4 K.-W. Kwon, "SHENVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture" 488-490, 2014

5 C.W. Smullen, "Relaxing non-volatility for fast and energy-efficient STT-RAM caches" 50-61, 2011

6 S. Datta, "Nonvolatile spin switch for Boolean and non-Boolean logic" 2012

7 N. Sakimura, "Nonvolatile Magnetic Flip-Flop for StandbyPower-Free SoCs" 2244-2250, 2009

8 S. Yamamoto, "Nonvolatile Delay Flip-Flop Based on Spin-Transistor Architecture" 2010

9 S. Li, "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures" 469-480, 2009

10 Y. Jiang, "Magnetic Tunnel Junction-Based Spin Register for Nonvolatile Integrated Circuits" 2917-2923, 2012

11 S. G. Narendra, "Leakage in Nanometer CMOS Technologies" Springer 2005

12 X. Fong, "KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spintransfer torque MRAM bit-cells" 51-54, 2011

13 M. Powell, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories" 90-95, 2000

14 권건우, "Energy Reduction in Asymmetric Write Operations of STT-MRAMs" 대한전자공학회 18 (18): 337-345, 2018

15 S. Borkar, "Design challenges of technology scaling" 23-29, 1999

16 F. Brglez, "Combinational profiles of sequential benchmark circuits" 1929-1934, 1989

17 S. Ikeda, "A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction" 2010

18 M. Hosomi, "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM" 459-462, 2005

19 M. Qazi, "A 3.4pJ FeRAM-enabled D flip-flop in 0.13um CMOS for nonvolatile processing in digital systems" 192-193, 2013