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      KCI등재 SCOPUS

      Implementation of Memristor Towards Better Hardware/Software Security Design

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      https://www.riss.kr/link?id=A107282622

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      다국어 초록 (Multilingual Abstract)

      The latest electronic devices are seeking much smaller CMOS devices but limitless scaling down of CMOS transistor leads to degradation in its performance. The classical security systems designed with CMOS devices are prone to physical and side-channel...

      The latest electronic devices are seeking much smaller CMOS devices but limitless scaling down of CMOS transistor leads to degradation in its performance. The classical security systems designed with CMOS devices are prone to physical and side-channel attacks. The missing element “Memristor” whose concept was proposed by Leon Chua is becoming the best choice for emerging hardware security design. Few characteristics of memristor which observed at the beginning seem to be problematic have turned into a blessing for security design and these characteristics are bi-directionality, process variation, non-volatility, and radiation hardness. Due to ultralow power consumption and high computational speed, memristors are drawing the attention of researchers as it also is useful in digital memory design, neuromorphic systems, logic circuits, and hardware security systems. In this manuscript, various memristor applications in hardware and software security systems will be focused on. It comprises a memristor-based physically unclonable function (PUF), which became novel security primitive. Memristor applications are also explained in a true random number generator by which the security of the digital transaction can be improved. The tamper detection circuits developed with memristors are capable to detect the tampering of the secret information in smart cards and therefore memristor-based tamper sensitive circuits are also briefed here to protect the secret data. Finally, the utilization of the memristor in the forensics, crypto architecture, and neuromorphic security systems are explained which will enhance the memristor applicability in the designing of advanced information protection digital circuits and systems.

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      참고문헌 (Reference)

      1 J. Singh, "enhanced nonlinear memristor model encapsulating stochastic dopant drift" 14 : 1-6, 2019

      2 J. Singh, "design and performance analysis of nano-scale memristor-based nonvolatile static random access memory" 16 (16): 798-805, 2018

      3 J. Singh, "Tunnel current model of asymmetric mim structure levying various image forces to analyze the characteristics of fi lamentary memristor" 125 (125): 203-213, 2019

      4 Y. N. Joglekar, "The elusive memristor : Properties of basic electrical circuits" 30 : 661-, 2009

      5 "The Embedded Security Challenge"

      6 C.-E. Yin, "Temperature-Aware Cooperative Ring Oscillator PUF" 2009

      7 J. Singh, "Temperature dependent analytical modeling and simulations of nanoscale memristor" Elsevier 21 (21): 862-868, 2018

      8 S. Kvatinsky, "TEAM:ThrEshold adaptive memristor model" 60 (60): 211-221, 2013

      9 K. Szot, "Switching the electrical resistance of individual dislocations in single-crystalline SrTiO3" 5 : 312-320, 2006

      10 H. Manem, "Stochastic gradient descent inspired training technique for a CMOS/Nano memristive trainable threshold gate array" 59 (59): 1051-1060, 2012

      1 J. Singh, "enhanced nonlinear memristor model encapsulating stochastic dopant drift" 14 : 1-6, 2019

      2 J. Singh, "design and performance analysis of nano-scale memristor-based nonvolatile static random access memory" 16 (16): 798-805, 2018

      3 J. Singh, "Tunnel current model of asymmetric mim structure levying various image forces to analyze the characteristics of fi lamentary memristor" 125 (125): 203-213, 2019

      4 Y. N. Joglekar, "The elusive memristor : Properties of basic electrical circuits" 30 : 661-, 2009

      5 "The Embedded Security Challenge"

      6 C.-E. Yin, "Temperature-Aware Cooperative Ring Oscillator PUF" 2009

      7 J. Singh, "Temperature dependent analytical modeling and simulations of nanoscale memristor" Elsevier 21 (21): 862-868, 2018

      8 S. Kvatinsky, "TEAM:ThrEshold adaptive memristor model" 60 (60): 211-221, 2013

      9 K. Szot, "Switching the electrical resistance of individual dislocations in single-crystalline SrTiO3" 5 : 312-320, 2006

      10 H. Manem, "Stochastic gradient descent inspired training technique for a CMOS/Nano memristive trainable threshold gate array" 59 (59): 1051-1060, 2012

      11 H. Fujisaka, "Stability theory of synchronized motion in coupled-oscillator systems" 69 (69): 32-47, 1983

      12 A. Oblea, "Silver chalcogenide-based memristor devices in Proceedings" 1-3, 2010

      13 K. -H. Jo, "Self-adaptive write circuit for low-power and variation-tolerant memristors" 9 (9): 675-678, 2010

      14 Chaofei Yang, "Security of Neuromorphic Computing:Thwarting Learning Attacks Using Memristor’s Obsolescence Effect" 16-, 2016

      15 S. Kannan, "Secure memristorbased main memory" 178-171, 2014

      16 Saini, "Secure Communication Using Memristor based Chaotic" 2014

      17 G. Khedkar, "RRAM motifs for mitigating diff erential power analysis attacks (DPA)" 88-93, 2012

      18 D. E. Holcomb, "Power-up SRAM state an identifying fi ngerprint and source of true random numbers" 58 (58): 1198-1210, 2009

      19 J Guajardo, "Physical unclonable functions and public-key crypto for FPGA IP protection" 189-195, 2007

      20 G. E. Suh, "Physical Unclonable Functions for Device Authentication and Secret Key Generation" 2007

      21 F. Alibart, "Pattern classifi cation by memristive crossbar circuits using ex situ and in situ training" 4 : 2072-, 2013

      22 J. C. Scott, "Nonvolatile memory elements based on organic materials" 19 : 1452-1463, 2007

      23 R. Waser, "Nanoionics-based resistive switching memories" 6 : 833-840, 2007

      24 J. Rajendran, "NanoPPUF: A memristor-based security primitive" 84-87, 2012

      25 J. Rajendran, "Nano meets security : Exploring nanoelectronic devices for security applications" 103 (103): 829-849, 2015

      26 Jeetendra Singh, "Modeling of mean barrier height levying various image forces of metal insulator metal structure to enhance the performance of conductive fi lament based memristor model" 17 (17): 268-275, 2018

      27 L. Chua, "Memristor-The missing circuit element" 18 (18): 507-519, 1971

      28 U. Chatterjee, "Memristor based Arbiter PUF: Cryptanalysis Threat and its Mitigation" 2016

      29 P. Koeberl, "Memristor PUFs: A new generation of memory-based physically Unclonable functions" 428-431, 2013

      30 B. Cambou, "Match-In-Place: A Novel Way to Perform Secure and Fast Users Authentication"

      31 R. Maes, "Intrinsic PUFs from Flip-fl ops on reconfi gurable devices" 2008

      32 A. Sawa, "Interface resistance switching at a few nanometer thick perovskite manganite active layers" 88 (88): 2321121-2321123, 2006

      33 B. Briggs, "Infl uence of copper on the switching properties of hafnium oxide-based resistive memory" 1337 : 857-, 2011

      34 F. Kotydek, "Improved ring oscillator PUF on FPGA and its properties" 47 : 1-9, 2016

      35 Nor Hashim, "Implementing Memristor in Ring Oscillators Based Random Number Generator" 2016

      36 R. Williams, "How we found the missing memristor" 45 (45): 28-35, 2008

      37 N. Beckmann, "Hardware-basedpublic-key cryptography with public physically unclonablefunctions" 5806 : 206-220, 2009

      38 S. S. Kumar, "Extended abstract: The butterfl y PUF protecting IP on every FPGA" 66-70, 2008

      39 W. Schindler, "Evaluation criteria for physical random number generators" 3 : 25-54, 2009

      40 H. Manem, "Design considerations for multilevel CMOS/Nano memristive memory" 8 (8): 61-622, 2012

      41 J. Singh, "Design and investigation of 7T2M NVSRAM with enhanced stability and temperature impact on store/restore energy" 27 (27): 1322-1328, 2019

      42 G. Suh, "Design and implementation of the AEGIS single-chip secure processor using physical random functions" 25-36, 2005

      43 Maxim Integrated, "DS28CN01: 1 KbitI2C/SMBus EEPROM With SHA-1 Engine"

      44 J. Singh, "Comparative Analysis of Memristor Model for Memories Design" 39 (39): 1-12, 2018

      45 L. Goux, "Coexistence of the bipolar and unipolar resistiveswitching modes in NiO cells made by thermal oxidation of Ni layers" 107 (107): 024512-, 2010

      46 N. B. Zhitenev, "Chemical modifi cation of the electronic conducting states in polymer nanodevices" 2 : 237242-, 2007

      47 N. Weste, "CMOS VLSI Design: A Circuits and Systems Perspective" Addison-Wesley 2010

      48 J. Rajendran, "An energy-effi cient memristive threshold logic circuit" 61 : 474-487, 2012

      49 Jeetendra Singh, "An accurate and generic window function for non-linear memristor model" Springer 18 (18): 640-647, 2019

      50 G. Rose, "A writetime based memristive PUF for hardware security applications" 830-833, 2013

      51 A. Maiti, "A robust physical unclonable function with enhanced challenge-response set" 7 (7): 333-345, 2012

      52 B. Sunar, "A provably secure true random number generator with built-in tolerance to active attacks" 56 : 109-119, 2007

      53 X. Wang, "2010 Spintronic memristor devices and application" 667-672, 2010

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2011-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2009-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2006-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2005-05-30 학회명변경 영문명 : 미등록 -> The Korean Institute of Electrical and Electronic Material Engineers KCI등재후보
      2005-05-30 학술지명변경 한글명 : Transactions on Electrical and Electroni -> Transactions on Electrical and Electronic Materials KCI등재후보
      2005-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2003-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.08 0.08 0.1
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.1 0.11 0.239 0.07
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