1 Woo Young Choi, "Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec" Institute of Electrical and Electronics Engineers (IEEE) 28 (28): 743-745, 2007
2 Evan O. Kane, "Theory of Tunneling" AIP Publishing 32 (32): 83-91, 1961
3 Arnab Biswas, "TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model" Elsevier BV 98 : 334-337, 2012
4 S. Dash, "Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate" 91 : 105-111, 2016
5 S. Safa, "Simulation-based study on the effect of inversion charge layer on triple material double gate Tunnel FET" 329-332, 2016
6 "Sentaurus Device User Guide, ver. G-2012.06"
7 S. W. Kim, "Investigation on hump effects of L-shaped tunneling filed-effect transistors" 1-2, 2012
8 Woojun Lee, "Influence of Inversion Layer on Tunneling Field-Effect Transistors" Institute of Electrical and Electronics Engineers (IEEE) 32 (32): 1191-1193, 2011
9 Nilay Dagtekin, "Impact of Super-Linear Onset, Off-Region Due to Uni-Directional Conductance and Dominant $\mathrm{C}_{\text {GD}}$ on Performance of TFET-Based Circuits" Institute of Electrical and Electronics Engineers (IEEE) 3 (3): 233-239, 2015
10 A. Mishra, "Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits" 1-4, 2013
1 Woo Young Choi, "Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec" Institute of Electrical and Electronics Engineers (IEEE) 28 (28): 743-745, 2007
2 Evan O. Kane, "Theory of Tunneling" AIP Publishing 32 (32): 83-91, 1961
3 Arnab Biswas, "TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model" Elsevier BV 98 : 334-337, 2012
4 S. Dash, "Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate" 91 : 105-111, 2016
5 S. Safa, "Simulation-based study on the effect of inversion charge layer on triple material double gate Tunnel FET" 329-332, 2016
6 "Sentaurus Device User Guide, ver. G-2012.06"
7 S. W. Kim, "Investigation on hump effects of L-shaped tunneling filed-effect transistors" 1-2, 2012
8 Woojun Lee, "Influence of Inversion Layer on Tunneling Field-Effect Transistors" Institute of Electrical and Electronics Engineers (IEEE) 32 (32): 1191-1193, 2011
9 Nilay Dagtekin, "Impact of Super-Linear Onset, Off-Region Due to Uni-Directional Conductance and Dominant $\mathrm{C}_{\text {GD}}$ on Performance of TFET-Based Circuits" Institute of Electrical and Electronics Engineers (IEEE) 3 (3): 233-239, 2015
10 A. Mishra, "Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits" 1-4, 2013
11 Pengyu Long, "Design and Simulation of GaSb/InAs 2D Transmission-Enhanced Tunneling FETs" Institute of Electrical and Electronics Engineers (IEEE) 37 (37): 107-110, 2016
12 Y. Zhong, "Current Degradation and Delay Analysis of Series-Connected Circuits Based on Novel TFET Design" 1-3, 2018
13 J. Knoch, "Chapter Eight - nanowire tunneling field-effect transistors" 94 : 273-295, 2015
14 Pei-Yu Wang, "Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure" Institute of Electrical and Electronics Engineers (IEEE) 15 (15): 74-79, 2016
15 Rajat Vishnoi, "An Accurate Compact Analytical Model for the Drain Current of a TFET From Subthreshold to Strong Inversion" Institute of Electrical and Electronics Engineers (IEEE) 62 (62): 478-484, 2015
16 C. Usha, "A tunneling FET exploiting in various structures and different models: A review" 1-6, 2015