Study on Bioplar and SCR-based ESD Protection Devices with High Robustness and Efficient Area using Floating Diffusion for High Voltage ICs

다국어 초록 (Multilingual Abstract)

This thesis presents a bipolar junction transistor (BJT)-based electrostatic discharge (ESD) protection device and silicon-controlled rectifier (SCR)-based ESD protection device. Both NPN bipolar transistors and silicon controlled rectifier (SCR) structures are widely used as high-voltage ESD clamp protection devices due to its high current driving capability and small footprint characteristics. However, these devices are not suitable for high-voltage technology because of the latch-up issue and the high trigger voltage. In this thesis, therefore, we propose a BJT-based ESD protection device that has a high robustness, low on-resistance, and a small footprint characteristics for high-voltage applications. Also, the SCR-based ESD protection device has high robustness and area efficiency for 250 V applications. The BJT-based device was implemented by combining an SCR device with a BJT. The device was designed with three parameters, and its characteristics can be optimized by adjusting those parameters. Our proposed device was fabricated with a 0.18, µm 60 V Bipolar CMOS DMOS (BCD) process, and its characteristics were verified through transmission-line pulse (TLP) tests, DC breakdown voltage measurements, and ESD zapping tests. In addition, the stacked structure was designed by using a unit device to apply the 60 V applications. From the experimental results, the unit device has a trigger voltage of 29.4 V and a holding voltage of 22.4 V. The proposed device exhibited an extremely low on-resistance characteristic of about 0.5 ohm. In addition, most of the unit devices passed the human-body model (HBM) 8 kV and the machine model (MM) 800 V. In the case of the stacking device, the holding and trigger voltages increased linearly with the number of stacks; the three-stack device passed the HBM 8000 V at the board level. Therefore, the proposed device will provide high reliability for high-voltage applications. The SCR-based device was designed through a 1.0 µm DMOS Silicon-On-Insulator (SOI) process. The measurement result of the proposed SCR device showed that the device has high current drivability of 10A or higher, holding voltage of 250 V higher, and trigger voltage of 460 V, and it passed 8 kV HBM. The proposed SCR device is properly designed for the IC characteristics, and the device has more than 70% area reduction and more than four times high robustness compared to PMOS 19-stack device. Through these studies, the proposed devices are suitable for high voltage IC characteristics, and they have high robustness and area efficient characteristics.