1 박재성, "양자컴퓨터 환경에서의 QCA 기반 내용주소화 메모리 셀 설계" 국제문화기술진흥원 6 (6): 521-527, 2020
2 LHB Sardinha, "Tcam/cam-qca : (ternary)content addressable memory using quantum-dot cellular automata" 46 (46): 563-571, 2015
3 J. C. Jeon, "Low Complexity QCA Universal Shift Register Design Using Multiplexer and D Flip-Flop Based on Electronic Correlations" 76 (76): 6438-6452, 2019
4 J. C. Jeon, "Designing nanotechnology QCA–multiplexer using majority function‑based NAND for quantum computing" 2020
5 N. Safoev, "Design of highperformance QCA incrementer/decrementer circuit based on adder/subtractor methodology" 72 : 111197-, 2020
6 M. B. Khosroshahy, "Design and evaluation of a 5-input majority gate-based content-addressable memory cell in quantum-dot cellular automata" 1-6, 2017
7 N. Safoev, "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata" 9 (9): 1036-, 2020
8 S. R. Heikalabad, "Content addressable memory cell in quantum-dot cellular automata" 163 : 140-150, 2016
9 C. D Thompson, "Area-time complexity for VLSI" 81-88, 1997
10 M. Balali, "A novel design of 5-input majority gate in quantum-dot cellular automata technology" 13-16, 2017
1 박재성, "양자컴퓨터 환경에서의 QCA 기반 내용주소화 메모리 셀 설계" 국제문화기술진흥원 6 (6): 521-527, 2020
2 LHB Sardinha, "Tcam/cam-qca : (ternary)content addressable memory using quantum-dot cellular automata" 46 (46): 563-571, 2015
3 J. C. Jeon, "Low Complexity QCA Universal Shift Register Design Using Multiplexer and D Flip-Flop Based on Electronic Correlations" 76 (76): 6438-6452, 2019
4 J. C. Jeon, "Designing nanotechnology QCA–multiplexer using majority function‑based NAND for quantum computing" 2020
5 N. Safoev, "Design of highperformance QCA incrementer/decrementer circuit based on adder/subtractor methodology" 72 : 111197-, 2020
6 M. B. Khosroshahy, "Design and evaluation of a 5-input majority gate-based content-addressable memory cell in quantum-dot cellular automata" 1-6, 2017
7 N. Safoev, "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata" 9 (9): 1036-, 2020
8 S. R. Heikalabad, "Content addressable memory cell in quantum-dot cellular automata" 163 : 140-150, 2016
9 C. D Thompson, "Area-time complexity for VLSI" 81-88, 1997
10 M. Balali, "A novel design of 5-input majority gate in quantum-dot cellular automata technology" 13-16, 2017
11 N. Safoev, "A Novel Controllable Inverter and Adder/Subtractor in Quantum-Dot Cellular Automata Using Cell Interaction Based XOR Gate" 222 : 111197-, 2020
12 M. Abdullah-Al-Shafi, "A New Structure for Random Access Memory Using Quantum-Dot Cellular Automata" 17 (17): 595-600, 2019