This thesis discusses a new and simplified type of processor. The aim of this thesis is to provide insight into time latency at the turn-around time in a time division duplexing (TDD) operation. A TDD system is satisfactory for the asymmetric data tra...
This thesis discusses a new and simplified type of processor. The aim of this thesis is to provide insight into time latency at the turn-around time in a time division duplexing (TDD) operation. A TDD system is satisfactory for the asymmetric data transmissions emphasized in internet services. In this system, the transition between when a frame is received and when a response is transmitted must be shortly defined for an effective use of radio resources. However, minimizing the inter frame space time requires a considerable amount of processing power.
The timing constraint is difficult to work within if using conven-tional implementation methods. A communication device for broadband wireless systems should consider the issue of processing latency in ter-minal systems. Despite great progress in digital and RF technologies, most devices continue to be limited in terms of processing power and memory capability. In addition, portable terminals should incorporate a small or even pocket sized dimension. Even when a high speed processor is applied, a real time operating system (RTOS) cannot meet the MAC re-quirements for time latency. In this regard, a designer may consider an optimized processor over a dedicated processor.
Accordingly, it is pertinent to consider the characteristics of burst-type traffic. Many of these processes are computation intensive and are constrained by hard real time deadlines. A pure hardware implementa-tion is advocated for a digital baseband block. The average throughput in a terminal is not high, although the MAC for broadband wireless com-munications can temporarily require a greater amount of processing power. Required in these cases is, therefore, a new processor that re-duces the turnaround time.
The turnaround time should be considered to allow interactions be-tween a transmitter and a receiver. With the aim of reducing the delay terms of the response generation, this thesis introduces a hardware en-gine to accelerate the processing operation. It also proposes a new accel-erator that prepares a preparative frame that is matched to the frame that is received on the other end. This solution represents the creation of a new processing architecture that reduces the turnaround time (from when a frame is received and when a response is transmitted - or vice versa) in a TDD operation.
The processing of burst-type traffic is constrained by hard real time deadlines. The inter frame space time in the media access control (MAC) of a TDD system is defined in standards as extremely short. This is also important in an 802.11 system, as the burden of the turnaround time is more critical compared to other types of broadband communications. This work observes the processing burden of network access traffic types and analyzes the processing time on a platform with an implementation of broadband wireless access processing.
The proposed MAC accelerator regulates the time critical processing problem. This processor incorporates portable terminal device-friendly architecture in order to support the processing of burst-type traffic. Thus the remaining processing power can be used for other applications in the terminal. This method is in the early stages of determining a protocol processing type that uses frame prediction in a TDD wireless communi-cation system. Finally, on the terminal side, it is believed that the func-tional blocks for this process of defining and developing can be reused for the development of the next generation of wireless communications.