In this paper, the architecture of 32 bit floating-point digital signal processors(TMS 32030, DSP96000) and implementation of FIR filtering by these processors have been studied. Finite word length effect and overflow during the process of accumulatio...
In this paper, the architecture of 32 bit floating-point digital signal processors(TMS 32030, DSP96000) and implementation of FIR filtering by these processors have been studied. Finite word length effect and overflow during the process of accumulation can be effectively eliminated by floating point digital signal processors. To increase the signal processing speed, these processors feature single cycle floating-point/integer multiplier, instruction cache or on-chip program RAM, multiple address buses and data buses, multiple address calculation units, extended precision registers and on-chip high speed memory block is suggested in this paper. In addition, circular buffering technique and multiply accamulate instruction with parallel data move have been suggested to simplify code implementation and to increase convolution speed.