FAULT MODELING AND SIMULATION FOR VLSI CIRCUITS

다국어 초록 (Multilingual Abstract)

An approach to a new transistor fault modeling and simulation for VLSI circuits are described. Our approach is mainly on how to derive an equivalent gate level logic circuit by using the worst-case behavior of the transistor circuit. Two types of faults are considered the conventional stuck-at faults on input/output lines and the transistor stuck faults in MOS transistors.
Our fault simulator can be used to simulate both good and faulty gates at the gate level and the transistor level including MOS/CMOS transmission gates, tristate gates, and BUS logic. On the basis of the proposed fault model, test generation and fault simulation procedures are described, and a number of experimental results are also shown.