X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

Park, Mingyo,Min, Byung-Wook Elsevier 2018 Solid-state electronics Vol.141 No.-

<P><B>Abstract</B></P> <P>This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm<SUP>2</SUP> without pads, which is 25% smaller than the T/R switch with stacked transistors.</P>

강성도 국부 변환 신축성 기판 위에 제작된 박막 트랜지스터 기반 변형률 센서

조영민,류경인,정성준 한국센서학회 2023 센서학회지 Vol.32 No.6

Stiffness-engineered stretchable substrate technology has been widely used to produce stretchable displays, transistors, and integratedcircuits because it is compatible with various flexible electronics technologies. However, the stiffness-engineering technology has neverbeen applied to transistor-based stretchable strain sensors. In this study, we developed thin-film transistor-based strain sensors on stiffness-engineered stretchable substrates. We designed and fabricated strain-sensitive stretchable resistors capable of inducing changes indrain currents of transistors when subjected to stretching forces. The resistors and source electrodes of the transistors were connectedin series to integrate the developed stretchable resistors with thin-film transistors on stretchable substrates by printing the resistors afterfabricating transistors. The thin-film transistor-based stretchable strain sensors demonstrate feasibility as strain sensors operating understrains of 0%–5%. This strain range can be extended with further investigations. The proposed stiffness-engineering approach willexpand the potential for the advancement and manufacturing of innovative stretchable strain sensors.

Enhanced transconductance in a double-gate graphene field-effect transistor

Hwang, Byeong-Woon,Yeom, Hye-In,Kim, Daewon,Kim, Choong-Ki,Lee, Dongil,Choi, Yang-Kyu Elsevier 2018 Solid-State Electronics Vol.141 No.-

<P><B>Abstract</B></P> <P>Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.</P> <P><B>Highlights</B></P> <P> <UL> <LI> A double-gate structure is adopted for a graphene transistor. </LI> <LI> Maximum transconductance is enhanced 50% by using the double-gate structure. </LI> <LI> Using a compact model, the enhanced transconductance is quantitatively explained. </LI> </UL> </P>

Sol-Gel derived Ga-In-Zn-O Semiconductor Layers for Solution-Processed Thin-Film Transistors

문주호,김동주,정선호,Jooho Moon,Chiyoung Park,Minhyon Jeon,Won-Chol Sin,Jinha Jung,Hyun-Jung Woo,Seung-Hyun Kim,Jowoong Ha 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.1

We have prepared a solution processed oxide semiconductor layer for thin-film transistors. The oxide semiconductor thin-film were prepared by spin coating a sol-gel precursor solution based on Ga and In-co-doped ZnO (GIZO). The sol-gel-derived GIZO film were uniform and have smooth surface morphology (rms. roughness ~0.7 nm). The device performance of the solution-processed thin-flm transistors was analyzed as a function of the doping concentration and the annealing temperature. The transistors annealed at 450 ℃ showed clear switching behavior and output characteristic with relatively high field effect mobility (~0.1 ㎠/V·s) and low threshold voltage (~5.4 V). Even when annealed at 300 ℃, they showed reasonable field effect mobility (~0.03 cm2/Vs) and a lower threshold voltage (~-0.2 V). Our findings demonstrate the feasibility of using sol-gel-based oxide semiconductor transistors for successful application to cost-effective and mass-producible display and optoelectronic devices with enhanced device performance. We have prepared a solution processed oxide semiconductor layer for thin-film transistors. The oxide semiconductor thin-film were prepared by spin coating a sol-gel precursor solution based on Ga and In-co-doped ZnO (GIZO). The sol-gel-derived GIZO film were uniform and have smooth surface morphology (rms. roughness ~0.7 nm). The device performance of the solution-processed thin-flm transistors was analyzed as a function of the doping concentration and the annealing temperature. The transistors annealed at 450 ℃ showed clear switching behavior and output characteristic with relatively high field effect mobility (~0.1 ㎠/V·s) and low threshold voltage (~5.4 V). Even when annealed at 300 ℃, they showed reasonable field effect mobility (~0.03 cm2/Vs) and a lower threshold voltage (~-0.2 V). Our findings demonstrate the feasibility of using sol-gel-based oxide semiconductor transistors for successful application to cost-effective and mass-producible display and optoelectronic devices with enhanced device performance.

조립형 박막 트랜지스터 모델링 프레임워크

정태호 한국반도체디스플레이기술학회 2017 반도체디스플레이기술학회지 Vol.16 No.3

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

Cho, B.,Yu, S.H.,Lee, M.H.,Lee, J.,Lee, J.Y.,Cho, J.H.,Kang, M.S. Elsevier Science 2014 ORGANIC ELECTRONICS Vol.15 No.12

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.

다양한 펄스 반복률에서의 NPN BJT (Bipolar Junction Transistor)의 파괴 특성에 관한 연구

방정주,허창수,이종원,Bang, Jeong-Ju,Huh, Chang-Su,Lee, Jong-Won 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.3

This paper examines the destruction behavior of NPN BJT (bipolar junction transistor) by repetition pulse. The injected pulse has a rise time of 1 ns and the maximum peak voltage of 2 kV. Pulse was injected into the base of transistor. Transistor was destroyed, current flows even when the base power is turned off. Cause the destruction of the transistor is damaged by heat. Breakdown voltage of the transistor is 975 V at single pulse, and repetition pulse is 525~575 V. Pulse repetition rate increases, the DT (destruction threshold) is reduced. Pulse Repetition rate is high, level of transistor destruction is more serious.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability

Kwon, Jimin,Takeda, Yasunori,Fukuda, Kenjiro,Cho, Kilwon,Tokito, Shizuo,Jung, Sungjune American Chemical Society 2016 ACS NANO Vol.10 No.11

<P>In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.</P>

Display Driver IC용 Amplifier Input Transistor의 Matching 개선

김현철,노용한,Kim, Hyeon-Cheol,Roh, Yong-Han 한국전기전자재료학회 2008 전기전자재료학회논문지 Vol.21 No.3

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

탄소나노튜브 기반 트랜지스터의 응용과 현황에 관한 연구

조근호 사단법인 인문사회과학기술융합학회 2019 예술인문사회융합멀티미디어논문지 Vol.9 No.11

탄소나노튜브 트랜지스터는 기존 실리콘 기반 트랜지스터의 한계로 받아들여지고 있는 5 nm보다 작은 크기로 반도체 소자의 소스와 드레인 사이를 만들 수 있어, 기존 반도체 소자보다 향상된 성능을 가진 반도체 소자를 기존 반도체 소자가 필요로 했던 면적보다 좁은 면적에 구현할 수 있을 것으로 기대되고 있다. 이는 가까운 미래에 기존 실리콘 기반 트랜지스터로 구성된 반도체 칩보다 빠르고 다양한 기능을 수행할 수 있는 탄소나노튜브 트랜지스터 기반 반도체 칩이 나올 수 있음을 의미한다. 이와 더불어, 탄소나노튜브 트랜지스터를 구성하는 탄소나노튜브의 기계적인 유연성과 친환경성은 기존 반도체 소자를 직접 적용하기 어려웠던 사물에 회로를 구현할 수 있도록 하여, 다양한 주변 사물로부터 광범위한 정보를 수집하고 처리해야하는 IoT 시대를 좀 더 적극적으로 대응하는데 큰 도움을 줄 수 있을 것으로 기대하고 있다. 본 논문에서는 최근 연구된 탄소나노튜브 기반 트랜지스터의 응용과 현황을 종합하고 분석하여 탄소나노튜브 트랜지스터의 다양한 가능성을 살펴보고자 한다. Carbon nanotube transistors can be made between source and drain of a semiconductor device with a size smaller than 5 nm, which is accepted as a limitation of the conventional silicon-based transistors. It is expected that the carbon naotube based device having improved performance than that of a conventional semiconductor device can be implemented in a smaller area than that required by the conventional semiconductor device. This means that, in the near future, carbon nanotube transistor-based semiconductor chips that can perform a variety of functions faster than conventional semiconductor chips composed of silicon-based transistors may be available. In addition, the mechanical flexibility and eco-friendly nature of the carbon nanotubes that make up the carbon nanotube transistors make it possible to implement circuits on various objects that have been difficult to directly apply to existing semiconductor devices, it is expected to be of great help in responding more actively to the era of IoT which must collect and process a wide range of information from various surrounding objects. In this paper, we examine the various possibilities of carbon nanotube transistors by collecting and analyzing the applications and current status of recently studied carbon nanotube-based transistors.