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직류링크 전류를 이용한 인터리브드 양방향 컨버터의 상전류 불균형 보상 방법
한정호(Jungho Han),최유현(Yuhyon Choi),송중호(Joongho Song) 한국조명·전기설비학회 2014 조명·전기설비학회논문지 Vol.28 No.8
This paper presents a compensation method of unbalanced phase currents in interleaved bi-directional converters. Phase currents in interleaved bi-directional converter are apt to be unbalanced due to circuit parameter error and switch operation difference. This problem causes the switch element failure and the reduced efficiency of the converter. Therefore, it is necessary that a certain balance control algorithm is provided in interleaved bi-directional converter system. In this paper, a balance control algorithm based on the circular chain control method is proposed. Further, in order to reduce the number of phase current sensors, this paper shows a simple method in which phase currents can be extracted indirectly through a DC-link current sensor in both charging and discharging modes. The validity and the effectiveness of the proposed phase currents balance control algorithm are illustrated through the simulation results.
Linearity improvement of UltraScale+ FPGA-based time-to-digital converter
김재원,정진호,최용,정지웅,이상원 한국원자력학회 2023 Nuclear Engineering and Technology Vol.55 No.2
Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale þ FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the ‘HU method’ (HU TDC) and with ‘both HU and MCT methods’ (HU-MCT TDC) were measured and compared to those of the TDC with ‘DDL alone’ (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.
Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs
Jun Yeon Won,Jae Sung Lee Institute of Electrical and Electronics Engineers 2016 IEEE transactions on instrumentation and measureme Vol.65 No.7
<P>This paper proposes a bin-width tuning method for a field-programmable gate array (FPGA)-based delay line for a time-to-digital converter (TDC). Changing the hit transitions and sampling patterns of the carry chain considering delays of the sum and carry-out bins can improve the bin-width uniformity and thus measurement precision. The proposed sampling method was evaluated and compared with the ordinary tapped-delay-line (TDL) method in three different types of FPGAs: Kintex-7, Virtex-6, and Spartan-6. The linearity, equivalent bin width, and measurement precision improved for all the evaluated FPGAs by adopting the proposed method. The measurement precision obtained using the simple TDL architecture is comparable with other complex TDC architectures. In addition, the proposed method improves bin-width uniformity and measurement precision while maintaining the advantages of TDL TDCs, that is, fast conversion rate and small resource usage. Furthermore, the enhanced linearity of the delay line can also improve other carry-chain-based FPGA-TDCs.</P>
High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches
LEE, Jaejun,LEE, Sungho,SONG, Yonghoon,NAM, Sangwook The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.12
<P>This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13µm standard CMOS technology and the experimental results agree well with the theory.</P>
중ㆍ대용량 STATCOM을 위한 새로운60-스텝 인버터 시스템
김기용,김태훈,배영상,최세완 전력전자학회 2005 전력전자학회 논문지 Vol.10 No.5
In this paper new 60-step inverter system for medium-to-large scale STATCOM is proposed and operating principle along with control method is detailed. A simple auxiliary circuit is employed to improve output voltage waveform of 12-step into 60-step. The proposed scheme could be a cost effective approach in high power application such as 10Mvar to 30Mvar STATCOM. Experimental results from a 2KVA laboratory prototype show validity of the proposed method. 본 논문에서는 새로운 이중접속 방식의 60-스텝 인버터를 제안하고 이를 이용한 대용량 STATCOM에 관하여 동작원리 및 제어방식을 기술하기로 한다. 기존의 12-스텝 인버터에 간단한 보조회로를 추가하여 출력전압의 파형을 60-스텝으로 개선하였다. 제안한 방식의 인버터는 커패시터의 전압분할이 필요하지 않아 간접제어 방식의 적용이 용이하며 10Mvar~30Mvar급 범위의 STATCOM에 적용하면 경제적이다. 2KVA급 시작품의 실험결과로부터 제안한 방식의 타당성을 입증하였다.
이중접속방식의 멀티스텝 인버터를 이용한 대용량 STATCOM의 개발
김태훈,배영상,최세완,이왕하 전력전자학회 2004 전력전자학회 논문지 Vol.9 No.1
In this paper a large scale STATCOM using double-connected multi-step inverter is proposed and operating principle along with control method is detailed. A simple auxiliary circuit including an interphase transformer is employed to improve output voltage waveform of 12-step into 36-step. The proposed scheme could be a cost effective approach in high power applications such as 10MVar to 30MVar STATCOM. Experimental results from a 2KVA laboratory prototype show validity of the proposed method. 본 논문에서는 이중접속 방식의 멀티스텝 인버터를 이용한 대용량 STATCOM에 관하여 동작원리 및 제어 방식을 기술하기로 한다. 기존의 12-스텝 인버터에 상간 변압기 및 간단한 보조회로를 이용하여 출력전압의 파형을 36-스텝으로 개선하였다. 이러한 방식의 인버터는 특히 10Mvar~30Mvar급 전후의 STATCOM에 적용하면 경제적이다. 2KVA급 STATCOM 시작품의 실험결과로부터 제안한 방식의 타당성을 입증하였다.