Analysis of Output Pulse of High Voltage and Nanosecond Blumlein Pulse Generator

Roh, Young-Su,Jin, Yun-Sik The Korean Institute of Electrical Engineers 2013 Journal of Electrical Engineering & Technology Vol.8 No.1

A high voltage and nanosecond Blumlein pulse generator has been developed to produce an output pulse whose voltage level is greater than 250 kV and pulse duration 5 ns. The generator consists of various components such as a charging circuit, a pulse transformer, and a spark gap switch. As a heart of the generator, a Blumlein pulse forming line has been constructed in the cylindrical form using three cylindrical aluminum electrodes that are placed concentrically. Unlike the ideal Blumlein line, the output pulse of an actual Blumlein line may be affected by stray inductances and capacitances of switching and charging components, thereby degrading the performance of the generator. In this paper, PSPICE simulations have been performed to examine effects of stray inductances and capacitances on waveforms of output pulses. Simulation results show that the pulse waveform is significantly distorted mainly by the stray inductance of the spark gap switch.

Analysis of Output Pulse of High Voltage and Nanosecond Blumlein Pulse Generator

Young-Su Roh,Yun-Sik Jin 대한전기학회 2013 Journal of Electrical Engineering & Technology Vol.8 No.1

A high voltage and nanosecond Blumlein pulse generator has been developed to produce an output pulse whose voltage level is greater than 250 kV and pulse duration 5 ns. The generator consists of various components such as a charging circuit, a pulse transformer, and a spark gap switch. As a heart of the generator, a Blumlein pulse forming line has been constructed in the cylindrical form using three cylindrical aluminum electrodes that are placed concentrically. Unlike the ideal Blumlein line, the output pulse of an actual Blumlein line may be affected by stray inductances and capacitances of switching and charging components, thereby degrading the performance of the generator. In this paper, PSPICE simulations have been performed to examine effects of stray inductances and capacitances on waveforms of output pulses. Simulation results show that the pulse waveform is significantly distorted mainly by the stray inductance of the spark gap switch.

130 ㎚ CMOS 공정을 이용한 UWB High-Band용 저전력 디지털 펄스 발생기

정창욱(Chang-Uk Jung),유현진(Hyun-Jin Yoo),어윤성(Yun-Seong Eo) 한국전자파학회 2012 한국전자파학회논문지 Vol.23 No.7

본 논문에서는 UWB의 6~10 ㎓ 주파수 대역을 위한 디지털 방식의 CMOS UWB 펄스 발생기를 제안하였다. 제안된 펄스 발생기는 매우 적은 전력 소모와 간단한 구조로 설계 및 구현되었다. 이 펄스 발생기는 가변되는 shunt capacitor 방식으로 구성된 CMOS delay line을 사용하여 중심 주파수를 제어할 수 있게 하였고, Gaussian Pulse Shaping 회로를 이용하여 FCC 등에서 제시하는 UWB 스펙트럼 규정을 만족할 수 있도록 설계하였다. 측정결과, 가변 가능한 중심 주파수는 4.5~7.5 ㎓까지 자유롭게 조절이 가능하였고, 펄스의 폭은 대략 1.5 ns였다. 그리고 10 ㎒의 PRF 조건에서 310 ㎷ pp의 크기의 펄스 신호를 보여주었다. 회로는 0.13 ㎛ CMOS 공정으로 제작되었고, 코어의 크기는 182×65 ㎛²로 매우 작은 크기로 설계되었으며, 평균 소모 전력은 1.5 V 전원을 사용하는 출력 buffer에서 11.4 ㎽를 소모하고, 이를 제외한 코어에서는 0.26 ㎽의 매우 작은 전력을 소모하고 있다. In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 ㎓) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 ㎓ to 7.5 ㎓ and pulse width is 1.5 ns and pulse amplitude is 310 ㎷ peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 ㎛ CMOS process with a core area of only 182×65 ㎛² and dissipates the average power of 11.4 ㎽ at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 ㎽ except for output buffer.

Pulse-Width Modulation Strategy for Common Mode Voltage Elimination with Reduced Common Mode Voltage Spikes in Multilevel Inverters with Extension to Over-Modulation Mode

Khoa-Dang Pham,Nho-Van Nguyen 전력전자학회 2019 JOURNAL OF POWER ELECTRONICS Vol.19 No.3

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

3레벨 4레그 PWM 컨버터의 커먼 모드 전압 저감

지승준(Seung-Jun Chee),고상기(Sanggi Ko),김현식(Hyeon-Sik Kim),설승기(Seung-Ki Sul) 전력전자학회 2014 전력전자학회 논문지 Vol.19 No.6

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called “f leg pole voltage” is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

Pulsed Voltage Converter with Bipolar Output Voltages up to 10 ㎸ for Dielectric Barrier Discharge

D. Tastekin,Q. K. Nguyen,A. Lunk,J. Roth-Stielow 전력전자학회 2011 ICPE(ISPE)논문집 Vol.2011 No.5

For pulsed power applications special pulsed voltage converters are needed. This paper presents an approach for a pulsed power converter, which generates bipolar output voltages up to 10 ㎸ with extremely fast voltage slopes and high repetition rates. The topology is based on a H-bridge with a 10 ㎸ dc-link. The output voltage and current of the pulsed voltage converter are adapted for the operation with Dielectric Barrier Discharge. To avoid the use of spark gaps due to their limited lifetime and thus to the lifetime of the converter, series stacked MOSFETs are used to realize a switch with a high blocking voltage. A balancing network for the series stacked MOSFETs is introduced as well as an adequate gate drive circuit. A matching method for the capacitive load is described, to achieve a maximum voltage slope at this capacitive load. To validate the theoretical considerations a prototype and measurements are presented.

A Proximity Coupling RF Sensor for Wrist Pulse Detection Based on Injection-Locked PLL

Byung-Hyun Kim,Yunseog Hong,Yong-Jun An,Sang-Gyu Kim,Hee-Jo Lee,Sung-Woo Kim,Seung-Bum Hong,Gi-Ho Yun,Jong-Gwan Yook Professional Technical Group on Microwace Theory a 2016 IEEE Transactions on Microwave Theory and Techniqu Vol. No.

<P>In this paper, a proximity coupling RF sensor based on injection-locked phase-locked loop (PLL) for wrist pulse detection is proposed. The sensor is composed of two main parts: a free-running oscillator and a PLL synthesizer containing a voltage-controlled oscillator. The free-running oscillator is built with a two-port microstrip line resonator (interdigital electrodes), which acts as part of a transducer that can transform the expansion or contraction of the radial artery into an impedance variation. Measurements show that the impedance variation of the resonator due to changes in the radial artery causes a frequency change of up to 0.74 MHz in the free-running oscillator. For the PLL part, the frequency change can be transformed to a variation in dc voltage by injection of the modulated signal from the wrist pulse into a phase-locked oscillator. The variation of the loop-control voltage, in one cycle of the pulse, is approximately 10-15 mV peak-to-peak. Our sensor is demonstrated to be an effective noncontact and noninvasive scheme for wrist pulse detection.</P>

Fast Voltage-Balancing Scheme for a Carrier-Based Modulation in Three-Phase and Single-Phase NPC Three-Level Inverters

Xi Chen,Shenghua Huang,Dong Jiang,Bingzhang Li 대한전기학회 2018 Journal of Electrical Engineering & Technology Vol.13 No.5

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC threelevel inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

Optimal pulse pattern with negative pulses and third harmonic mixed injection

Qinqing Zhang,Wenxiang Song,Tianqing Shui,Hongzhang Lyu 전력전자학회 2022 JOURNAL OF POWER ELECTRONICS Vol.22 No.3

Adding negative pulses into a neutral-point clamped three-level inverter is an optimal pulse pattern (OPP) that can help restrain the neutral-point (NP) voltage fluctuation. However, this method can also cause the current harmonic distortion to be increased so that it becomes difficult to quantify the negative pulse width. Third harmonic injection can suppress neutralpoint potential fluctuation without increasing the switching frequency and it can also be automatically eliminated. Based on current harmonic minimization pulse width modulation (CHMPWM), a new optimal pulse pattern containing negative pulses and third harmonics is presented, which can inhibit NP voltage. Regarding the re-expression of the fundamental voltage expression, the optimal third harmonic content can be determined by constructing the analytical relationship between the fundamental voltage and the neutral-point current under the harmonic voltage. Combining this with a fitness function, sequence quadratic programming (SQP) is utilized to solve the new switching angles, which means that the CHMPWM is injected by negative pulses and third harmonics. Through simulations and experiments on a three-level inverter with a resistance-inductance load, it is verified that the proposed method can effectively suppress the voltage fluctuation at the neutral-point of the DC bus while taking the current harmonic distortion rate into account.

고전압 펄스 발생 장치의 특성에 관한 시뮬레이션 연구

김영주(Young-Ju Kim),신주희(Ju-Hee Shin) 한국조명·전기설비학회 2012 조명·전기설비학회논문지 Vol.26 No.12

The high-voltage pulse generator is consist of transformers of fundamental wave and harmonic waves, and shunt capacitances. The pulse has the fundamental wave and the harmonic waves that have been increased as a series circuit by the transformers to make high voltage pulse. This paper shows the high-voltage pulse generator simulation using a circuit program with experiment data. In the equivalent circuit, magnetized inductances and loss resistances which affect output voltage, have been obtained. The output capacitor circuits have characteristics of band pass. The output voltages of the pulse width 50% and 25%(PWM) were obtained. The output of the high-voltage pulse generator is 2.5kHz, 1.8kV.