Overview of Real-Time Java Computing

Yu Sun,Wei Zhang 한국정보과학회 2013 Journal of Computing Science and Engineering Vol.7 No.2

This paper presents a complete survey of recent techniques that are applied in the field of real-time Java computing. It focuses on the issues that are especially important for hard real-time applications, which include time predictable garbage collection, worst-case execution time analysis of Java programs, real-time Java threads scheduling and compiler techniques designed for real-time purpose. It also evaluates experimental frameworks that can be used for researching real-time Java. This overview is expected to help researchers understand the state-of-the-art and advance the research in real-time Java computing.

Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore Processors

Yu Liu,Wei Zhang 한국정보과학회 2015 Journal of Computing Science and Engineering Vol.9 No.2

Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.

Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore Processors

Liu, Yu,Zhang, Wei Korean Institute of Information Scientists and Eng 2015 Journal of Computing Science and Engineering Vol.9 No.2

Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.

고속 정밀 로봇 제어를 위한 실시간 중앙 집중식 소프트 모션 제어 시스템

정일균,김정훈 대한임베디드공학회 2013 대한임베디드공학회논문지 Vol.8 No.6

In this paper, we propose a real-time centralized soft motion control system for high speed and precision robot control. The system engages EtherCAT as high speed industrial motion network to enable force based motion control in real-time and is composed of software-based master controller with PC and slave interface modules. Hard real-time control capacity is essential for high speed and precision robot control. To implement soft based real time control, The soft based master controller is designed using a real time kernel (RTX) and EtherCAT network, and servo processes are located in the master controller for centralized motion control. In the proposed system, slave interface modules just collect and transfer all sensor information of robot to the master controller via the EtherCAT network. It is proven by experimental results that the proposed soft motion control system has real time controllability enough to apply for various robot control systems.

Overview of Real-Time Java Computing

Sun, Yu,Zhang, Wei Korean Institute of Information Scientists and Eng 2013 Journal of Computing Science and Engineering Vol.7 No.2

This paper presents a complete survey of recent techniques that are applied in the field of real-time Java computing. It focuses on the issues that are especially important for hard real-time applications, which include time predictable garbage collection, worst-case execution time analysis of Java programs, real-time Java threads scheduling and compiler techniques designed for real-time purpose. It also evaluates experimental frameworks that can be used for researching real-time Java. This overview is expected to help researchers understand the state-of-the-art and advance the research in real-time Java computing.

Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability

Zhang, Wei,Ding, Yiqiang Korean Institute of Information Scientists and Eng 2014 Journal of Computing Science and Engineering Vol.8 No.1

Time-predictability of computing is critical for hard real-time and safety-critical systems. However, currently there is no metric available to quantitatively evaluate time-predictability, a feature crucial to the design of time-predictable processors. This paper first proposes the concept of architectural time-predictability, which separates the time variation due to hardware architectural/microarchitectural design from that due to software. We then propose the standard deviation of clock cycles per instruction (CPI), a new metric, to measure architectural time-predictability. Our experiments confirm that the standard deviation of CPI is an effective metric to evaluate and compare architectural time-predictability for different processors.

Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability

Wei Zhang,Yiqiang Ding 한국정보과학회 2014 Journal of Computing Science and Engineering Vol.8 No.1

Time-predictability of computing is critical for hard real-time and safety-critical systems. However, currently there is no metric available to quantitatively evaluate time-predictability, a feature crucial to the design of time-predictable processors. This paper first proposes the concept of architectural time-predictability, which separates the time variation due to hardware architectural/microarchitectural design from that due to software. We then propose the standard deviation of clock cycles per instruction (CPI), a new metric, to measure architectural time-predictability. Our experiments confirm that the standard deviation of CPI is an effective metric to evaluate and compare architectural time-predictability for different processors.

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance

Yu Liu,Wei Zhang 한국정보과학회 2014 Journal of Computing Science and Engineering Vol.8 No.4

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable twolevel scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratchpad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance

Liu, Yu,Zhang, Wei Korean Institute of Information Scientists and Eng 2014 Journal of Computing Science and Engineering Vol.8 No.4

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors

Wu, Lan,Ding, Yiqiang,Zhang, Wei Korean Institute of Information Scientists and Eng 2014 Journal of Computing Science and Engineering Vol.8 No.1

In this paper, we quantitatively compare two different time-predictable multicore cache architectures, separate and statically-partitioned caches, through extensive simulation. Current research trends primarily focus on partitioned-cache architectures in order to achieve time predictability for hard real-time multicore based systems, and our experiments reveal that separate caches actually lead to much better performance and energy efficiency when compared to statically-partitioned caches, and both of them are adequate for timing analysis for real-time multicore applications.