A Core Compact Model for Multiple-Gate Junctionless FETs

Jae Hur,Dong-Il Moon,Ji-Min Choi,Myeong-Lok Seol,Ui-Sik Jeong,Chang-Hoon Jeon,Yang-Kyu Choi Institute of Electrical and Electronics Engineers 2015 IEEE transactions on electron devices Vol. No.

<P>A core model for multiple-gate junctionless FETs (Mug-JL-FETs) is proposed. The derived charge model is obtained via assumptions of simple potential profile for different types of Mug-JL-FETs. It was found that the linear potential approach is not accurate enough for a double-gate (DG) JL-FET, whereas it was reasonably precise for a DG inversion-mode FET. This discrepancy arises from their different operating mechanisms. Thus, the parabolic potential assumption, which is intuitively close to an actual potential profile in the Mug-FETs, was applied. As a consequence, two different formulas of the charge model in terms of depletion charges, gate capacitance, and capacitance inside the channel were found: one for a tetragonal shape of a cross-sectional channel based on a Cartesian coordinate and the other for a circular shape of a cross-sectional channel based on a cylindrical coordinate. Moreover, the proposed approach was applied for a realistically shaped channel, which is close to elliptic geometry, with a circular profile at the top and bottom parts of the channel and a rectangular profile at the center part of the channel. By applying the decoupling method reported previously, a drain current model, which is extended from the above-mentioned charge model, was also obtained.</P>

Complementary FET로 열어가는 반도체 미래 기술

김상훈,이성현,이왕주,박정우,서동우,S.H. Kim,S.H. Lee,W.J. Lee,J.W. Park,D.W. Suh 한국전자통신연구원 2023 전자통신동향분석 Vol.38 No.6

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

Jae Hur,Byung-Hyun Lee,Min-Ho Kang,Dae-Chul Ahn,Tewook Bang,Seung-Bae Jeon,Yang-Kyu Choi IEEE 2016 IEEE electron device letters Vol.37 No.5

<P>A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.</P>

밀리미터파 대역 제2고조파 고효율 생성을 위한 부하 임피던스의 최적화 방법

최영규(Young-Kyu Choi) 대한전기학회 2011 전기학회논문지 Vol.60 No.8

The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.

Performance Analysis of the Gate All Around Nanowire FET with Group III–V Compound Channel Materials and High-k Gate Oxides

Shashank Shandilya,Charu Madhu,Vijay Kumar 한국전기전자재료학회 2023 Transactions on Electrical and Electronic Material Vol.24 No.3

The increasing demand for faster and energy efficient electronics has forced the researchers to develop more power and performance efficient integrated circuits. For this purpose, the overall size of the transistor needs to be scaled down to its very limit. Transistor scaling and performance are not only limited to overall transistor design but also to the material of the channel that is being used. In order to make a performance efficient transistor, not only is a new transistor design needed but replacement of conventional channel material i.e., silicon needs to be done. In this work, a 2-D Numerical simulation model of nanowire FET with GAA technology was carried out at 22 nm gate length using an open-source nanoscale simulation tool MUGFET. Then a study of the performance parameters of this NW-GAAFET with Silicon and Group III-V compound semiconductor channel materials and High-k gate oxides has been performed. The electrical performance parameters, drain induced barrier lowering (DIBL), subthreshold swing (SS), and on/off current ratio (Ion/Ioff) are extracted and validated through comparative analysis with previous high performance GAA nanowire FETs.

GaAs MES FET를 사용한 M/W대 저잡음 증폭기의 설계

박종백 조선대학교 생산기술연구소 1991 生産技術硏究 Vol.13 No.1

To improve receiving sensibility and reliability it was experimented using Low Noise Amplifier which is Frequency band 6GHz. Gain 30dB and Noise Figure 3dB. As a result it could be seen that the threshold level is going down to 7.8dB and it decreases the outage time 83.5% in the 83kms distance betwen M/W channel like a section from Moo-dueng station to Mang-un station.

Growth and Device Applications of GaAs and InGaAs Quantum Wires on Patterned Substrates

Mutsuo Ogura 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.3

A GaAs/AlGaAs quantum wire (QWR) with optical characteristics superior to those of a quantum well (QWL) was realized by employing metal-organic chemical-vapor deposition (MOCVD) selective growth on a patterned substrate by using flow-rate-modulation epitaxy (FME) and tertiary butyl arsine (TBA) as a V element precursor. A narrow (25 × 10 nm2) InGaAs/InP QWR was also fabricated on a (311)A InP V-groove substrate by using hydrogen-assisted molecular-beam-epitaxy (MBE) selective growth, the QWR exhibited enhanced negative differential resistance effects even at temperatures near room temperature. The lasing spectra of a Fabry-Perot QWR laser, together with the optical and electronic characteristics of these QWRs, indicate an extension of the coherent electron wave function along the QWR and the formation of sharp density states as a result of reduced dimensionality. As regards QWR devices, a QWR field-effect transistor (FET) was found to work as a highly sensitive photo-detector. This is because the QWR and the surrounding QWL work as a small charge-sensitive amplifier and a photo-absorbing region, respectively. A gain-coupled distributed feedback (DFB) laser was realized by using a high-density buried quantum wire (QWR) array, that restricted minority carrier difusion along the QWR within a ridge. A GaAs/AlGaAs quantum wire (QWR) with optical characteristics superior to those of a quantum well (QWL) was realized by employing metal-organic chemical-vapor deposition (MOCVD) selective growth on a patterned substrate by using flow-rate-modulation epitaxy (FME) and tertiary butyl arsine (TBA) as a V element precursor. A narrow (25 × 10 nm2) InGaAs/InP QWR was also fabricated on a (311)A InP V-groove substrate by using hydrogen-assisted molecular-beam-epitaxy (MBE) selective growth, the QWR exhibited enhanced negative differential resistance effects even at temperatures near room temperature. The lasing spectra of a Fabry-Perot QWR laser, together with the optical and electronic characteristics of these QWRs, indicate an extension of the coherent electron wave function along the QWR and the formation of sharp density states as a result of reduced dimensionality. As regards QWR devices, a QWR field-effect transistor (FET) was found to work as a highly sensitive photo-detector. This is because the QWR and the surrounding QWL work as a small charge-sensitive amplifier and a photo-absorbing region, respectively. A gain-coupled distributed feedback (DFB) laser was realized by using a high-density buried quantum wire (QWR) array, that restricted minority carrier difusion along the QWR within a ridge.

5.8GHz 무선 랜용 서브 하모닉 저항성 혼합기의 설계

유홍길,김완식,강정진,이종악,Yoo, Hong-Gil,Kim, Wan-Sik,Kang, Jeong-Jin,Lee, Jong-Arc 한국전기전자학회 2004 전기전자학회논문지 Vol.8 No.1

본 논문은 5.8 GHz 무선 랜용 서브 하모닉 저항성 혼합기를 설계하였다. 서브 하모닉 저항성 혼합기는 서브 하모닉 혼합기와 저항성 혼합기의 장점이 합쳐진 구조이다. 서브 하모닉 저항성 혼합기는 LO의 고조파 성분과 RF를 혼합하여 IF주파수를 얻는다. 그래서 기존의 혼합기보다 낮은 LO 주파수를 사용이 가능하다. 그리고 서브 하모닉 저항성 혼합기는 GaAs FET의 unbiased 채널 저항을 사용하여 주파수 혼합하므로 낮은 IMD를 특성을 갖는다. 제작된 서브 하모닉 저항성 혼합기의 변환손실은 LO 신호전력이 13 dBm일 때, 10.67 dB이다. 그리고 혼합기의 IIP3는 21.5 dBm이다. In this paper, it is designed for 5.8GHz Wireless LAN sub harmonic resistive mixer. Sub harmonic resistive mixer is constituted by advantage of sub harmonic mixer and resistive mixer. Sub harmonic resistive mixers mix harmonics of LO with RF and obtain IF frequency. Therefore, it was possible to use decreasing LO frequency than conventional mixers. And, Sub harmonic resistive mixer has low IMD because of using unbiased channel resistance of GaAs FET. When LO power is 13dBm, the conversion loss of manufactured sub harmonic resistive mixer is 10.67 dB. And IIP3 of mixer is 21.5dBm.

Comparative Study of Single and Double Gate All Around Cylindrical FET Structures for High-K Dielectric Materials

Rajveer Kaur,Balwinder Singh 한국전기전자재료학회 2021 Transactions on Electrical and Electronic Material Vol.22 No.4

The performance of conventional MOSFET deteriorates because of the short channel effects that appears when it is scaled into nm regime. The existing techniques like channel scaling, variations in the work function implemented on a MOSFET could no longer confront these limitations which demand for the necessity of some upgraded devices and materials that would overcome these shortcomings and offer ameliorate performance. Two experimentally based devices gate all around (GAA) FET and double gate all around (DGAA) FET are modeled and compared at 10 nm and 20 nm respectively In this paper, the effect of scaling the gate length, oxide thickness and variations in the drain to source voltage utilizing two different gate dielectrics for a single and double GAA cylindrical FET on their respective device performance in terms of drive current (I ON ), leakage current (I OFF ), switching speed (I ON /I OFF ) and subthreshold swing. The study reveals that with a thinner gate oxide, less gate length, less drain to source voltage and with an additional core gate utilizing high-k dielectric materials, the device achieves a better subthreshold slope, higher value of ON-state current, larger ON/OFF current ratio, lesser OFF-state current and lesser power consumption.

The design and realization of a highly linear power amplifier module for a WiMAX/WiBro (802.16e) base station

Kim, Do-Gyun,Choi, Doo-Hun,Moon, Yon-Tae,Baek, Dong-Hyun,Baek, Kwang-Hyun,Choi, Young-Wan Wiley Subscription Services, Inc., A Wiley Company 2010 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS - Vol.52 No.9

<P>We have designed and realized a highly linear power amplifier module (PAM) for a WiMAX/WiBro base station using a simple linearization method. To improve the linearity of the PAM, we use large-signal intermodulation distortion (IMD) sweet spots, which are part of the inherent properties of power transistors. These IMD sweet spots are determined by the device technologies and the bias voltage. Our PAM consists of a drive stage and a power stage. Two amplifiers are used in the drive stage, a GaAs field effect transistor (GaAs FET) and a laterally diffused metal oxide semiconductor. The linearity of the PMA can be maximally improved by the large-signal IMD sweet spots, which are tuned by the bias voltage of the GaAs FET at the signal power input of the drive stage. Using this method, the measured adjacent channel leakage ratio and power consumption efficiency of the PAM are improved by 2.9 dBc and 5.2%, respectively. The measured error vector magnitude of the PAM is only 1.45. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1952–1955, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25374</P>