인코더-디코더 모델에서 잠재 벡터의 분류 성능 분석

강규창,배창석 한국차세대컴퓨팅학회 2023 한국차세대컴퓨팅학회 논문지 Vol.19 No.2

This paper compares and analyzes the classification performance of latent vectors in the encoder-decoder model. A typical encoder-decoder model, such as an autoencoder, transforms the encoder input into a latent vector and feeds it into the decoder. In this process, the encoder-decoder model learns to produce an decoder output similar to the encoder input. We can consider that the latent vector of the encoder-decoder model is well preserved by abstracting the characteristics of the encoder input. Further, it is possible to apply to unsupervised learning, if the latent vector guarantees a sufficient distance between clusters in the feature space. In this paper, the classification performance of latent vectors is analyzed as a basic study for applying latent vectors in encoder-decoder models to unsupervised and continual learning. The latent vectors obtained by the stacked autoencoder and 2 types of CNN-based autoencoder are applied to 4 kinds of classifiers including KNN and random forest. Experimental results show that the latent vector using the CNN-based autoencoder with a dense layer (about 97%) shows superior classification performance by up to 2% compared to the result of the stacked autoencoder (about 95%). Based on the results in this paper, it is possible to extend the latent vector obtained by using a CNN-based auto-encoder with dense layer to unsupervised learning. 본 논문에서는 인코더-디코더 모델 (encoder-decoder model)에서 잠재 벡터 (latent vector)의 분류 성능을 비교 분석한다. 오토인코더와 같은 일반적인 인코더-디코더 모델은 인코더 입력을 잠재 벡터로 변환하고 이를 디코더에 입력하여 인코더 입력과 유사한 출력을 생성하도록 학습한다. 이와 같은 인코더-디코더 모델의 잠재 벡터는 인코더 입력의 특징을 추상화하여 잘 보존한다고 고려할 수 있다. 나아가 잠재 벡터가 특징 공간에서 클러스터들 사이에서 구분이 가능한 거리를 보장한다면 이를 비지도 학습에 적용하는 것이 가능하다. 본 논문에서는 인코더-디코더 모델에서의 잠재 벡터를 비지도 학습 및 점진적 학습에 적용하기 위한 기초 연구로서 잠재 벡터의 분류 성능을 분석한다. 이를 위해 스택트 오토인코더 (stacked autoencoder)와 2가지 종류의 CNN (Convolutional Neural Network) 기반 오토인코더를 바탕으로 각각 구해지는 잠재 벡터를 KNN (K-Nearest Neighbor)과 랜덤 포레스트 (random forest)를 포함하는 4가지 종류의 분류기에 적용한다. 실험 결과 완전 연결 계층 (fully connected or dense layer)를 가지는 CNN 기반의 오토인코더를 사용한 결과 평균 정확률은 약 97%이고 스택트 오토인코더의 결과는 약 95%로 2% 정도 우수한 분류 성능을 보이는 것을 확인할 수 있다. 본 논문에서의 연구를 바탕으로 완전 연결 계층을 가지는 CNN 기반의 오토 인코더를 이용하여 구해지는 잠재 벡터를 비지도 학습에 적용하는 것으로 확장하는 것이 가능하다.

고 처리율 병렬 터보 복호기 설계

이원호(Won-Ho Lee),박희민(Heemin Park),임종석(Chong S. Rim) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.11

Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

Boseok Jung,Taesung Kim,Hanho Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SDBCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 ㏈ coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-㎚ CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

VLSI Implementation of High Throughput Turbo Decoder for Mobile WiMAX Modem

오상목,이정우 에스케이텔레콤 (주) 2009 Telecommunications Review Vol.19 No.5

In this paper, we propose the architecture for the high-throughput turbo (CTC) decoder used in the Mobile WiMAX modem. The proposed CTC decoder uses Min-Log-MAP algorithm, unsigned bits for quantization of metrics, and efficient architecture for finding a minimum value and preventing overflows in the computation of state metrics. Instead of using two stages of comparators to find a minimum value, which is conventional in the state metric computation unit, the proposed CTC decoder replaces the second stage of comparators by AND gates for the Most Significant Bits (MSB) of the first stage outputs. Thanks to the reduction of the complexity resulting from the efficient architecture, the CTC decoder achieves high operating frequency. The proposed CTC decoder architecture allows parallel computation of forward state metrics and backward state metrics. As a result, the number of cycles required to complete one iteration of decoding are reduced by half compared with those of conventional CTC decoders. A permuter, used as interleaver and deinterleaver alternatively, is designed to reduce by half the cycle required for data writing and thus to be compatible with the parallel computation of state metrics. The proposed CTC decoder is implemented by Samsung 0.18um CMOS process. A single CTC decoder designed by proposed architecture supports the operating frequency of 275 MHz and the throughput of 68.3 Mbps. It is verified that the throughput requirement of Mobile WiMAX standard is satisfied by using two CTC decoders in a parallel manner.

이중 분기 디코더를 사용하는 복소 중첩 U-Net 기반 음성 향상 모델

황서림,박성욱,박영철 한국음향학회 2024 韓國音響學會誌 Vol.43 No.2

본 논문에서는 이중 분기 디코더를 갖는 복소 중첩 U-Net 기반의 새로운 음성 향상 모델을 제안하였다. 제안된모델은 음성 신호의 크기와 위상 성분을 동시에 추정할 수 있도록 복소 중첩 U-Net으로 구성되며, 디코더는 스펙트럼사상과 시간 주파수 마스킹을 각각의 분기에서 수행하는 이중 분기 디코더 구조를 갖는다. 이때, 이중 분기 디코더 구조는 단일 디코더 구조에 비하여, 음성 정보의 손실을 최소화하면서 잡음을 효과적으로 제거할 수 있도록 한다. 실험은음성 향상 모델 학습을 위해 보편적으로 사용되는 VoiceBank + DEMAND 데이터베이스 상에서 이루어졌으며, 다양한 객관적 평가 지표를 통해 평가되었다. 실험 결과, 이중 분기 디코더를 사용하는 복소 중첩 U-Net 기반 음성 향상 모델은 기존의 베이스라인과 비교하여 Perceptual Evaluation of Speech Quality(PESQ) 점수가 0.13가량 증가하였으며, 최근 제안된 음성 향상 모델들보다도 높은 객관적 평가 점수를 보였다. This paper proposes a new speech enhancement model based on a complex nested U-Net with a dual-branch decoder. The proposed model consists of a complex nested U-Net to simultaneously estimate the magnitude and phase components of the speech signal, and the decoder has a dual-branch decoder structure that performs spectral mapping and time-frequency masking in each branch. At this time, compared to the single-branch decoder structure, the dual-branch decoder structure allows noise to be effectively removed while minimizing the loss of speech information. The experiment was conducted on the VoiceBank + DEMAND database, commonly used for speech enhancement model training, and was evaluated through various objective evaluation metrics. As a result of the experiment, the complex nested U-Net-based speech enhancement model using a dual-branch decoder increased the Perceptual Evaluation of Speech Quality (PESQ) score by about 0.13 compared to the baseline, and showed a higher objective evaluation score than recently proposed speech enhancement models.

An Efficient List Successive Cancellation Decoder for Polar Codes

Piao, Zheyan,Kim, Chan-Mi,Chung, Jin-Gyun The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.5

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

Jung, Boseok,Kim, Taesung,Lee, Hanho The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

파이프라인 기반 다중윈도방식의 비터비 디코더를 이용한 채널 코딩 시스템의 구현

서영호,김동욱,Seo Young-Ho,Kim Dong-Wook 한국정보통신학회 2005 한국정보통신학회논문지 Vol.9 No.3

본 논문에서는 시분할 방식을 확장하여 윈도를 통해 비터비 복호화 되는 단위를 다중으로 버퍼링하고 병렬적으로 처리하는 비터비 복호화기를 구현한다. 연속적으로 입력되는 신호를 복호화 길이의 배수로 버퍼링한 후 이를 고속의 비터비 복호화기 셀을 이용하여 병렬적으로 복호화를 수행한다. 비터비 복호화기 셀의 사용수에 비례하여 데이터 출력율을 얻을 수 있는데 입력 버퍼의 프로그래밍 및 수정에 따라서 이러한 동작을 만족시킬 수 있다. 구현된 비터비 복호화기 셀은 해밍 거리 계산을 위한 HD 블록, 각 상태의 계산을 위한 CM 블록, 비교를 위한 CS 블록, 그리고 trace-back을 위한 TB 블록 및 LIFO 등으로 구성된다. 비터비 복호화기 셀은 ALTERA의 APEX20KC EP20K600CB652-7 FPGA에서 $1\%(351;cell)$의 LAB(Logic a..ay block)를 사용하여 최대 139MHz에서 안정적으로 동작할 수 있었다. 또한 비터비 복호화기 셀과 입출력 버퍼링을 위한 회로를 포함한 전체 비터비 복호화기는 약 $23\%$의 자원을 사용하면서 최대 1Gbps의 데이터 출력율을 가질 수 있도록 설계하였다. In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

An Efficient List Successive Cancellation Decoder for Polar Codes

Zheyan Piao,Chan-Mi Kim,Jin-Gyun Chung 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

High-performance Syndrome-based SD-BCH Decoder Architecture using Hard-decision Kernel

Taesung Kim,Hanho Lee 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.6

This paper proposes a high-performance, low-complexity, soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and its efficient design techniques. The proposed SD-BCH decoder not only uses the test syndrome computation, but also non-iteration processes. The proposed (1020, 990) SD-BCH decoder achieves a 0.75 dB higher coding gain compared to the (1020, 990) hard-decision BCH (HD-BCH) decoder. The proposed SD-BCH decoder was designed and implemented using the 65-nm CMOS technology. The synthesis results show that the proposed SD-BCH decoder architecture with serial structure (P = 1) has 24.7K gate count, which leads to a 69% reduction in hardware complexity compared to the previous SD-BCH decoder architecture.