CMOS의 설계 파라미터 및 Cascode단의 변화에 따른 Time-Domain Temperature Sensor 특성에 관한 연구

우솔아,김진세,금종민,경신수,성만영 한국과학기술원 반도체설계교육센터 2015 IDEC Journal of Integrated Circuits and Systems Vol.1 No.1

This paper presents low power and high speed on-chip temperature sensor only using two ring-oscillators which have different CMOS delay characteristics, counters and Time-to-Digital Converters (TDC) to maintain the performance benefit of CMOS digital circuit. This novel temperature sensor does not require any bias circuits or reference external clocks. The novel temperature sensor measures the delay variations between the temperature-dependent signal generator and the temperature-independent signal generator according to temperature. The generating two signals is sensed by TDC. But, temperature sensor of TDC cells, which was used to measure the delay time of two CMOS delay characteristics and convert to digital outputs, occupies large chip area. To overcome this problem, we designed an advanced temperature sensor using Coarse-Fine TDC. Also, it has a higher resolution than existing temperature sensor. After checking the performance of the temperature sensor using a HSPICE simulation, the chip was manufactured using the Dongbu 0.11μm CMOS process and verified. 본 논문에서는 서로 다른 CMOS Delay 특성을 갖는 2개의 링 오실레이터와 카운터, Time-to-Digital Converter(TDC)를 이용한 Digital On-Chip 온도 감지 센서를 설계하였다. 본 논문에서 제안한 온도 감지 센서는 신호 발생 단과 신호 출력 단으로 구성된다. 신호 발생 단은 CMOS로 구성된 링 오실레이터와 카운터로 구성되어 있고, CMOS의 Cascode단을 쌓음으로써 온도에 대한 민감도를 제어할 수 있다. 따라서 온도에 민감한 링 오실레이터와 온도에 민감하지 않은 링 오실레이터를 설계하고, 카운터를 이용하여 두 신호의 펄스 너비를 증폭시켰다. 신호 발생 단에서 발생된 신호는 신호 출력 단으로 인가된다. 신호 출력 단은 TDC로 구성하여 온도 변화를 디지털 코드로 감지할 수 있다. 온도 감지 센서는 -20∼120℃를 감지할 수 있도록 설계하였다. 또한 제안한 온도 감지 센서에서는 Chip 면적을 최소화하기 위해 Coarse TDC와 Fine TDC를 이용하여 설계하였다. 이를 통해 고 분해능을 갖는 온도 감지 센서를 설계하였고, HSPICE simulation을 통해 온도 감지 센서의 성능을 검증하였다. Chip은 동부 0.11um CMOS 공정으로 제작하여 측정하였다.

Design of a hybrid SAR-cyclic ADC with gain-error calibration

조성훈,이병근 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.1

Low-power consumption and medium resolution analog-to-digital converters (ADCs) operate at several tens of MS/s. These are crucial factors for portable wireless communication applications. In this paper, SAR-assisted cyclic ADC features the low-power merit of successive approximation (SAR) ADC and small chip area of cyclic ADC. It improves an intrinsic limitation of ADCs conversion speed. The power consumption of the operational amplifier for cyclic ADC is reduced dramatically by using a new simple gain-error calibration technique. The MSB 4-b is converted by cyclic ADC and it only needs 2 cycles by multiplying digital to analog converter (MDAC) operation. Residue voltage generated at the end of the 2nd cycle conversion of cyclic ADC is converted by 6-b SAR operation.

Design of RF CMOS Transceiver for Wireless Data Communication of Three-Dimensional Integrated Circuit Applications

신후영,문동우,이창현,이미림,박창근 한국과학기술원 반도체설계교육센터 2016 IDEC Journal of Integrated Circuits and Systems Vol.2 No.2

In this study, a wireless type of chip-to-chip communication(WCC) technology is proposed as the next generation of three-dimensional(3D) semiconductor technology. To demonstrate the feasibility of the technology, we design a transceiver and receiver for wireless chip-to-chip communication method. The transceiver part for WCC circuit is designed using the conventional cross-coupled oscillator structure. To reduce the distortion of the signal, we input the data using the cascade structure. The receiver part for WCC circuit consists of coil. To confirm the characteristic of the proposed transceiver and receiver coil structures, we performed electromagnetic simulation. From the simulation results, the possibility of proposed wireless data transfer system was verified. The proposed wireless data transfer system has been designed using CMOS process. In simulation, the frequency of input data is 100 MHz and the peak-to-peak voltage of the input signal is 2 V. The peak-to-peak voltage of output signal is approximately 1.2 V and oscillation frequency is 1.75 GHz. The simulation result is shown that the transmitter part is transmitting signal which has only difference of 0.08 ns. Also it was found that wireless transceiver system has power consumption about 40%. In measurement result, data input setup 1MHz, and other setup is equal to that of the simulation. From the measured results, we successfully verify the feasibility of the proposed structure.

A 5-5.8 GHz Sub-2 dB NF CMOS Low Noise Amplifier with Bandwidth Extension and Noise Optimization Techniques

김동명,임동구 한국과학기술원 반도체설계교육센터 2020 IDEC Journal of Integrated Circuits and Systems Vol.6 No.2

A 5-5.8 GHz sub-2 dB noise figure (NF) CMOS low noise amplifier (LNA) with bandwidth extension and noise optimization techniques is proposed for WiFi applications. The proposed LNA was based on the cascode feedback topology for broadband input impedance matching characteristic, and adopted the double-stacked LC resonators as an output load in order to extend the gain-bandwidth from 5 to 5.8 GHz. In addition, the input matching network was designed to provide the optimum source impedance for the minimum noise figure (NFmin) over wide frequency range (5-5.8 GHz) using the source-pull simulation. Owing to the proposed noise optimization technique, the NF of the LNA can be close to NFmin over wide operating frequency range. The proposed LNA was designed using a 65-nm CMOS process. It showed a NF of less than 2 dB, a power gain (S21) of greater than 15 dB, and an input and output return loss (S11 and S22) of less than -10 dB over 5-5.8 GHz in the post-layout simulation. The simulated 2 dB gain bandwidth and input-referred third-order intercept point (IIP3) were 1399 MHz and -4.1 dBm, respectively, with dc power consumption of 7.4 mW.

A 1.2V 30 MS/s SAR ADC with Foreground Capacitor Calibration

주현규,이세원,이민재 한국과학기술원 반도체설계교육센터 2019 IDEC Journal of Integrated Circuits and Systems Vol.5 No.2

– In this paper, a successive approximation register (SAR) ADC with foreground capacitor calibration is presented. In order to overcome the drawback of SAR architecture with low-power consumption, several techniques are adopted such as high-speed latch, three-stage comparator, reference-less architecture, custom metal-oxide-metal (MOM) capacitor, and foreground capacitor calibration. The design methodology and measurement procedure is presented in detail. The prototype ADC is fabricated in a 65 nm CMOS process, and it achieves signal-to-noise and distortion ratio (SNDR) over 60 dB at sampling frequency of 30 MS/s under 1.2 V supply voltage. The power consumption is 1.1 mW, and the chip area of the core ADC is 0.045 mm2.

A WR 3.4 x12 Frequency Multiplier Chain Based on InP HBT Technology

임기현,유중환,손희강,김도윤,이재성 한국과학기술원 반도체설계교육센터 2022 IDEC Journal of Integrated Circuits and Systems Vol.8 No.2

In this work, a x12 frequency multiplier chain has been developed in a 250-nm InP HBT technology for operation in the WR3.4 frequency band. The multiplier chain is composed of three frequency multipliers: a V-band frequency tripler, a D-band frequency doubler, and a WR3.4 frequency doubler. The V-band cascode frequency tripler exhibited a maximum output power of 0.83 dBm with a bandwidth of 59 - 72 GHz, while the D-band bootstrapped Gilbert-cell frequency doubler showed a maximum output power of 6.13 dBm with a bandwidth of 140 - 164 GHz. With the WR3.4 push-push frequency doubler, a maximum output power of 0.5 dBm was obtained with a bandwidth of 278 - 325 GHz. The fully integrated multiplier chain exhibited a saturation output power of 1.6 dBm at 300 GHz and a peak conversion gain of -3.6 dB at 3.5-dBm input power. The circuit operated over a frequency range of 246 - 318 GHz with up to 4.3-dB in-band output power variation. The total DC power consumption was 131mW.

Two-negative feedback loop PLL with frequency voltage converter loop

문대현,최영식 한국과학기술원 반도체설계교육센터 2019 IDEC Journal of Integrated Circuits and Systems Vol.5 No.4

- To reduce the phase noise and jitter of the conventional PLL, the proposed PLL uses frequency voltage converter (FVC). The inner negative feedback loop consisting of a voltage controlled oscillator (VCO) and a frequency voltage converter is nested inside a conventional outer PLL loop. When the output voltage (VCO input voltage) of the loop filter changes, the output voltage of the FVC changes in the opposite direction at a much higher sampling frequency in the negative feedback looped VCO. Thus, whenever the VCO output frequency varies, the FVC works as a compensator and it results in VCO noise reduction. It improves the phase noise characteristic and the stability of PLL. It has been simulated and proved by HSPICE in a CMOS 0.18μm 1.8V process. Measurement result of the two-negative feedback loop PLL fabricated in a one-poly six-metal 0.18μm CMOS process shows approximately 20dB improvement at 1MHz offset from 1GHz carrier frequency.

Counter-Based Frequency Discriminator for Fine Dust Sensor

박선의,박한기,김주엽,방주은,신유환,최재혁 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

This work presents a counter-based frequency discriminator for a fine dust sensor. Detecting the frequency variations of MEMS resonator according to the fine dust concentration, the proposed frequency discriminator provides digital codes which represents the frequency variations. Since the proposed frequency discriminator is based on the CMOS process, it achieved extremely small area and low power of 0.3 mW, which facilitates the integration into portable devices. The proposed counter-based frequency discriminator covers the input frequency range of 1.6 to 2.4 GHz with a resolution of 50 kHz. Since it has a flexible divider, its resolution and detection speed can be flexibly changed.

Analysis of the TEG Maximum Power Point Tracking Operation with Continuously Scalable-Conversion-Ratio SC Converter

김현진,김철우 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

This paper analyzes the output power of the thermoelectric generator (TEG) and continuously scalable-conversion-ratio SC converter for achieving low-power maximum power point tracking (MPPT) with switched-capacitor (SC) converter. In state-of-the-art SC energy harvesting interfaces, they transfer harvested power inefficiently due to fixed conversion ratios. Therefore, the proposed MPPT method harvest power based on the conventional open circuit voltage method, without additional open circuit voltage sampling period. The proposed energy harvesting converter is designed in a 180 nm CMOS process and is measured to prove that the power can be transferred properly with the analyzed power conversion modes.

An Evaluation and Comparison of State-of-the-Art Flip-Flops for Low-Power Applications

강경훈,정완영 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

Flip-Flop (FF) is the basic block of sequential digital circuits, which has a significant impact on the speed, power, and stability of digital systems. Reducing the power consumption of FFs is an attractive solution for attaining good energy efficiency of digital systems. However, the conventional TGFF (Transmission-gate flip-flop) consumes excessive dynamic power at clock inverters even though the data transition does not occur. To eliminate redundant clock transitions, some techniques are applied. This paper analyzes and compares recently published low-power FFs in 65 nm CMOS.