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Antecedents of Accepting Disruptive Innovation: The Perspective of Value Congruence
CUI, Yuan,ZHANG, Tingting,KIM, Seungwoon,FENG, Shi Korea Distribution Science Association 2021 The Journal of Asian Finance, Economics and Busine Vol.8 No.2
Originating in value congruence theory, this study aims to give a clear understanding of the transformation process of consumers from incumbent technology to disruptive innovation technology. Moreover, the moderating effect of personal innovativeness in the process of consumers' switching to disruptive innovation is investigated. This study combines value congruence with expectation-disconfirmation theory, technology-switching theory, and the personal innovativeness of the disruptive innovation product, explaining why consumers have transformed from an incumbent product into a disruptive innovation. Data was collected through a questionnaire from 280 smartphone users in China. The respondents were mainly potential consumers who had never bought Redmi phones, namely, a smart product owned by the renowned Chinese company Xiaomi. The hypothesis of the research model is based on the example of the Redmi smartphone, which has been confirmed by existing smartphone users in China. Through investigation, the results of multivariable regression analysis show the decisive variables that influence consumer intentions, and we analyze the role of personal innovativeness in moderating between dissatisfaction with the incumbent product and purchase intention of a product based on disruptive innovation. The findings of this study can provide a certain reference for the sustainable growth of Xiaomi and the development of new products.
A sequential triggering technique in cascaded current source for low power 12-b D/A converter
Cui, Zhi-Yuan,Choi, Ho-Yong,Cho, Tae-Won,Kim, Nam-Soo Emerald Group Publishing Limited 2011 Microelectronics international Vol.28 No.1
<B>Purpose</B> - The purpose of this paper is to introduce a low power digital-to-analog converter (DAC) by using a sequential triggering technique in cascaded current source. <B>Design/methodology/approach</B> - The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12-b 150-MS/s DAC has been integrated in a single-poly four-metal 0.35?µm CMOS process. <B>Findings</B> - Compared with conventional cell array in 12-b 150-MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB. <B>Originality/value</B> - This paper presents a new operation method of cell array in a current-steering digital-to-analog converter (DAC) to reduce the power consumption significantly.
A 10-bit Current-steering DAC in 0.35-μm CMOS Process
Cui, Zhi-Yuan,Piao, Hua-Lan,Kim, Nam-Soo The Korean Institute of Electrical and Electronic 2009 Transactions on Electrical and Electronic Material Vol.10 No.2
A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.
Influential Factors for SMEs of Environmentally Friendly Management in Chinese Distribution Industry
Yuan CUI,Youjian BAO,Yunwei CAI,Seung-Woon KIM 한국유통과학회 2022 유통과학연구 Vol.20 No.4
Purpose: Environmental pollution problems have become more and more serious, how to effectively protect the environment has become a hot spot of concern to all sectors of society. The way to solve this problem is environmentally friendly management. However, theoretical perspectives and research frameworks of existing research on environmentally friendly management are still unclear. This study aims to examine how the CEO’s beliefs for SMEs of Chinese distribution industry affect the environmentally friendly management based on institutional theory. Research design, data, and methodology: This paper collected data from 215 SMEs in China distribution industry and conducted a series of data analysis and hypothesis testing based on an institutional theory perspective using Amos and SPSS to verify the effects of regulatory pressure, normative pressure, and imitation pressure on firms environmentally friendly management. Results: Through the analysis, this paper tests that normative pressure and imitative pressure have a positive effect on CEO’s beliefs. However, regulatory pressure did not have a significant effect on beliefs of CEO. Meanwhile, the degree of CEO’s beliefs has a positive effect on environmentally friendly management in Chinese distribution SMEs. Conclusions: Theoretical contributions, practical implications, and future research directions are discussed.
Removal of High Density Impulse Noise of Aerial Insulator Image
Cui Kebin,Li Baoshu,Yuan Jinsha,Wang Ping 보안공학연구지원센터(IJSIP) 2014 International Journal of Signal Processing, Image Vol.7 No.6
Aiming at the impulse noise generated in capturing the images of insulator on power lines, a denoising method based on peer groups is proposed. The center pixel variance σcenter is defined, the minimum of neighborhood variance and center σmin is treated as threshold σmin and the peer group is determined by comparing the relation between absolute value of gray value difference and σmin . According to the size of peer group and its complement set, center pixel is estimated when noisy pixels exist in the neighborhood window. Otherwise, the size of window is adjusted adaptively and center pixel is estimated on the basis of mean value of non-noisy pixels within adjusted window. The experimental results show that the method can get a higher peak signal to noise ratio, IEF and SSIM when there is high density impulse noise in an image.
Low Power 10-b 250Msample/s CMOS Cascaded Folding and Interpolating A/D Converter
CUI, Zhi-Yuan,JIN, Yong-Gao,KIM, Nam-Soo,CHOI, Ho-Yong The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.8
<P>This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225mW at the sampling speed of 250Msample/s and the power supply of 3.3V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.</P>
Application of a low-glitch current cell in 10-bit CMOS current-steering DAC
Cui, Zhi-Yuan,Choi, Joong-Ho,Kim, Yeong-Seuk,Kim, Shi-Ho,Kim, Nam-Soo Emerald Group Publishing Limited 2009 Microelectronics international Vol.26 No.3
<B>Purpose</B> - The purpose of this paper is to describe the application of low-glitch current cell in a digital to analog converter (DAC) to reduce the clock-feedthrough effect and achieve a low power consumption. <B>Design/methodology/approach</B> - A low-glitch current switch cell is applied in a ten-bit two-stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock-feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35µm complementary metal-oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation. <B>Findings</B> - Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68?mW at the sampling frequency of 100?MHz. <B>Originality/value</B> - Comparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock-feedthrough effect.
Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter
Cui, Zhi-Yuan,Kim, Nam-Soo,Lee, Hyung-Gyoo,Kim, Kyoung-Won The Korean Institute of Electrical and Electronic 2007 Transactions on Electrical and Electronic Material Vol.8 No.1
A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.